stm32_eth.c 25.9 KB
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/*
 * (C) Copyright 2011
 *
 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * STM32 F2 Ethernet driver
 */

#include <config.h>

/*
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 * Define DEBUG to enable debug() messages in this module
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 */
#undef DEBUG

#include <common.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include <asm/errno.h>

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#include <asm/arch/stm32.h>
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#include <asm/arch/stm32f2_gpio.h>

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#if defined(CONFIG_STM32_SYS_CLK_HSI)
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# error "Can't run MAC with this CLK configuration."
#endif

/*
 * Device name
 */
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#define STM32_MAC_NAME			"STM32_MAC"
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/*
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 * STM32 MAC/DMA definitions
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 */
/*
 * MAC registers base
 */
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#define STM32_MAC_BASE			(STM32_AHB1PERIPH_BASE + 0x8000)
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/*
 * MACCR reg fields
 */
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#define STM32_MAC_CR_RE			(1 << 2)	/* Received enable    */
#define STM32_MAC_CR_TE			(1 << 3)	/* Transmitter enable */
#define STM32_MAC_CR_DM			(1 << 11)	/* Duplex mode	      */
#define STM32_MAC_CR_FES		(1 << 14)	/* Fast Eth speed     */
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/*
 * MACMIIAR reg fields
 */
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#define STM32_MAC_MIIAR_MB		(1 << 0)	/* MII busy	      */
#define STM32_MAC_MIIAR_MW		(1 << 1)	/* MII write	      */
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#define STM32_MAC_MIIAR_CR_BIT		2		/* Clock range	      */
#define STM32_MAC_MIIAR_CR_MSK		0x7
#define STM32_MAC_MIIAR_CR_DIV42	0x0		/* 60-100 MHz	      */
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#define STM32_MAC_MIIAR_CR_DIV62	0x1		/* 100-168 MHz	      */
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#define STM32_MAC_MIIAR_CR_DIV16	0x2		/* 20-35 MHz	      */
#define STM32_MAC_MIIAR_CR_DIV26	0x3		/* 35-60 MHz	      */
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#define STM32_MAC_MIIAR_MR_BIT		6		/* MII register	      */
#define STM32_MAC_MIIAR_MR_MSK		0x1F
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#define STM32_MAC_MIIAR_PA_BIT		11		/* PHY address	      */
#define STM32_MAC_MIIAR_PA_MSK		0x1F
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/*
 * DMABMR reg fields
 */
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#define STM32_MAC_DMABMR_SR		(1 << 0)	/* Software reset     */
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#define STM32_MAC_DMABMR_PBL_BIT	8		/* Burst length	      */
#define STM32_MAC_DMABMR_PBL_MSK	0x3F
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#define STM32_MAC_DMABMR_RTPR_BIT	14		/* Rx:Tx priority rat.*/
#define STM32_MAC_DMABMR_RTPR_MSK	0x3
#define STM32_MAC_DMABMR_RTPR_1_1	0x0		/* 1 : 1	      */
#define STM32_MAC_DMABMR_RTPR_2_1	0x1		/* 2 : 1	      */
#define STM32_MAC_DMABMR_RTPR_3_1	0x2		/* 3 : 1	      */
#define STM32_MAC_DMABMR_RTPR_4_1	0x3		/* 4 : 1	      */
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#define STM32_MAC_DMABMR_FB		(1 << 16)	/* Fixed burst	      */
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#define STM32_MAC_DMABMR_RDP_BIT	17		/* RX DMA PBL	      */
#define STM32_MAC_DMABMR_RDP_MSK	0x3F
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#define STM32_MAC_DMABMR_USP		(1 << 23)	/* Use separate PBL   */
#define STM32_MAC_DMABMR_AAB		(1 << 25)	/* Adr-aligned beats  */
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/*
 * DMASR reg fields
 */
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#define STM32_MAC_DMASR_TBUS		(1 << 2)	/* Tx buf unavailable */
#define STM32_MAC_DMASR_RBUS		(1 << 7)	/* Rx buf unavailable */
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/*
 * DMAOMR reg fields
 */
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#define STM32_MAC_DMAOMR_SR		(1 << 1)	/* Start/stop rx      */
#define STM32_MAC_DMAOMR_ST		(1 << 13)	/* Start/stop tx      */
#define STM32_MAC_DMAOMR_FTF		(1 << 20)	/* Flush tx FIFO      */
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/*
 * DMA transmit buffer descriptor bits
 */
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#define STM32_DMA_TBD_DMA_OWN		(1 << 31)	/* DMA/CPU owns bd    */
#define STM32_DMA_TBD_LS		(1 << 29)	/* Last segment	      */
#define STM32_DMA_TBD_FS		(1 << 28)	/* First segment      */
#define STM32_DMA_TBD_TCH		(1 << 20)	/* 2nd address chained*/
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/*
 * DMA receive buffer descriptor bits
 */
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#define STM32_DMA_RBD_DMA_OWN		(1 << 31)	/* DMA/CPU owns bd    */
#define STM32_DMA_RBD_FL_BIT		16		/* Frame length	      */
#define STM32_DMA_RBD_FL_MSK		0x3FFF
#define STM32_DMA_RBD_FS		(1 << 9)	/* First descriptor   */
#define STM32_DMA_RBD_LS		(1 << 8)	/* Last descriptor    */
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#define STM32_DMA_RBD_RCH		(1 << 14)	/* 2nd address chained*/
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/*
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 * STM32 SYSCFG definitions
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 */
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#define STM32_SYSCFG_BASE		(STM32_APB2PERIPH_BASE + 0x3800)
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/*
 * PMC reg fields
 */
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#define STM32_SYSCFG_PMC_SEL_BIT	23		/* MII/RMII selection */
#define STM32_SYSCFG_PMC_SEL_MSK	0x1
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#define STM32_SYSCFG_PMC_SEL_MII	0
#define STM32_SYSCFG_PMC_SEL_RMII	1
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/*
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 * STM32 RCC MAC specific definitions
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 */
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#define STM32_RCC_AHB1RSTR_MAC		(1 << 25)	/* Reset MAC	      */
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#define STM32_RXX_ENR_SYSCFG		(1 << 14)	/* SYSCFG clock	      */
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#define STM32_RCC_ENR_ETHMACEN		(1 << 25)	/* Ethernet MAC clock */
#define STM32_RCC_ENR_ETHMACTXEN	(1 << 26)	/* Ethernet Tx clock  */
#define STM32_RCC_ENR_ETHMACRXEN	(1 << 27)	/* Ethernet Rx clock  */
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/*
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 * Different timeouts
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 */
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#define STM32_PHY_READ_TIMEOUT		2500	/* x 100 usec = 250 ms */
#define STM32_PHY_WRITE_TIMEOUT		2500	/* x 100 usec = 250 ms */
#define STM32_PHY_AUTONEG_TIMEOUT	100000	/* x 100 usec = 10 s */
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#define STM32_MAC_TX_TIMEOUT		1000000	/* x 1 usec = 1000 ms */
#define STM32_MAC_INIT_TIMEOUT		20000	/* x 100 usec = 2 s */
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/*
 * MAC, MMC, PTP, DMA register map
 */
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struct stm32_mac_regs {
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	u32	maccr;		/* MAC configuration			      */
	u32	macffr;		/* MAC frame filter			      */
	u32	machthr;	/* MAC hash table high			      */
	u32	machtlr;	/* MAC hash table low			      */
	u32	macmiiar;	/* MAC MII address			      */
	u32	macmiidr;	/* MAC MII data				      */
	u32	macfcr;		/* MAC flow control			      */
	u32	macvlantr;	/* MAC VLAN tag				      */
	u32	rsv0[2];
	u32	macrwuffr;	/* MAC remote wakeup frame filter	      */
	u32	macpmtcsr;	/* MAC PMT control and status		      */
	u32	rsv1;
	u32	macdbgr;	/* MAC debug				      */
	u32	macsr;		/* MAC interrupt status			      */
	u32	macimr;		/* MAC interrupt mask			      */
	u32	maca0hr;	/* MAC address 0 high			      */
	u32	maca0lr;	/* MAC address 0 low			      */
	u32	maca1hr;	/* MAC address 1 high			      */
	u32	maca1lr;	/* MAC address 1 low			      */
	u32	maca2hr;	/* MAC address 2 high			      */
	u32	maca2lr;	/* MAC address 2 low			      */
	u32	maca3hr;	/* MAC address 3 high			      */
	u32	maca3lr;	/* MAC address 3 low			      */
	u32	rsv2[40];
	u32	mmccr;		/* MMC control				      */
	u32	mmcrir;		/* MMC receive interrupt		      */
	u32	mmctir;		/* MMC transmit interrupt		      */
	u32	mmcrimr;	/* MMC receive interrupt mask		      */
	u32	mmctimr;	/* MMC transmit interrupt mask		      */
	u32	rsv3[14];
	u32	mmctgfsccr;	/* MMC transmitted good frms after single col */
	u32	mmctgfmsccr;	/* MMC transmitted good frms after more col   */
	u32	rsv4[5];
	u32	mmctgfcr;	/* MMC transmitted good frames counter	      */
	u32	rsv5[10];
	u32	mmcrfcecr;	/* MMC received frames with CRC error counter */
	u32	mmcrfaecr;	/* MMC received frames with alignment error   */
	u32	rsv6[10];
	u32	mmcrgufcr;	/* MMC received good unicast frames counter   */
	u32	rsv7[334];
	u32	ptptscr;	/* PTP time stamp control		      */
	u32	ptpssir;	/* PTP subsecond increment		      */
	u32	ptptshr;	/* PTP time stamp high			      */
	u32	ptptslr;	/* PTP time stamp low			      */
	u32	ptptshur;	/* PTP time stamp high update		      */
	u32	ptptslur;	/* PTP time stamp low update		      */
	u32	ptptsar;	/* PTP time stamp addend		      */
	u32	ptptthr;	/* PTP target time high			      */
	u32	ptpttlr;	/* PTP target time low			      */
	u32	rsv8;
	u32	ptptssr;	/* PTP time stamp status		      */
	u32	ptpppscr;	/* PTP PPS control			      */
	u32	rsv9[564];
	u32	dmabmr;		/* DMA bus mode				      */
	u32	dmatpdr;	/* DMA transmit poll demand		      */
	u32	dmarpdr;	/* DMA receive poll demand		      */
	u32	dmardlar;	/* DMA receive descriptor list address	      */
	u32	dmatdlar;	/* DMA transmit descriptor list address	      */
	u32	dmasr;		/* DMA status				      */
	u32	dmaomr;		/* DMA operation mode			      */
	u32	dmaier;		/* DMA interrupt enable			      */
	u32	dmamfbocr;	/* DMA missed frame and buffer overflow	      */
	u32	dmarswtr;	/* DMA receive status watchdog timer	      */
	u32	rsv10[8];
	u32	dmachtdr;	/* DMA current host transmit descriptor	      */
	u32	dmachrdr;	/* DMA current host receive descriptor	      */
	u32	dmachtbar;	/* DMA current host transmit buffer address   */
	u32	dmachrbar;	/* DMA current host receive buffer address    */
};
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#define STM32_MAC			((volatile struct stm32_mac_regs *) \
					STM32_MAC_BASE)
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/*
 * SYSCFG register map
 */
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struct stm32_syscfg_regs {
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	u32	memrmp;		/* Memory remap				      */
	u32	pmc;		/* Peripheral mode configuration	      */
	u32	exticr[4];	/* External interrupt configuration	      */
	u32	rsv0[2];
	u32	cmpcr;		/* Compensation cell control		      */
};
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#define STM32_SYSCFG			((volatile struct stm32_syscfg_regs *) \
					STM32_SYSCFG_BASE)
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/*
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 * STM32 ETH Normal DMA buffer descriptors
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 */
struct stm_eth_dma_bd {
	volatile u32			stat;	/* Status		      */
	volatile u32			ctrl;	/* Control, and buffer length */
	volatile u8			*buf;	/* Pointer to buffer	      */
	volatile struct stm_eth_dma_bd	*next;	/* Pointer to next BD in chain*/
};

/*
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 * STM32 ETH device
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 */
struct stm_eth_dev {
	/*
	 * Standard ethernet device
	 */
	struct eth_device		netdev;

	/*
	 * PHY settings
	 */
	u32				phy_id;
	u32				phy_adr;

	/*
	 * DMA buffer descriptors, and index of last processed buf:
	 * - have one Tx buffer descriptor;
	 * - have CONFIG_SYS_RX_ETH_BUFFER rx buffer descriptors.
	 */
	volatile struct stm_eth_dma_bd	tx_bd;
	volatile struct stm_eth_dma_bd	rx_bd[PKTBUFSRX];
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	s32				rx_bd_idx;
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	/*
	 * ETH DMAed buffers:
	 * - send requested buffers directly, i.e. have no local storage;
	 * - receive buffers have length of 1536B (> max eth frm len)
	 */
	volatile u8			rx_buf[PKTBUFSRX][PKTSIZE_ALIGN];
};
#define to_stm_eth(_nd)	container_of(_nd, struct stm_eth_dev, netdev)

/*
 * Ethernet GPIOs:
 *
 * ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1
 * ETH_MDIO -------------------------> PA2
 * ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7
 * ETH_PPS_OUT ----------------------> PB5
 * ETH_MII_TXD3 ---------------------> PB8
 * ETH_MDC --------------------------> PC1
 * ETH_MII_TXD2 ---------------------> PC2
 * ETH_MII_TX_CLK -------------------> PC3
 * ETH_MII_RXD0/ETH_RMII_RXD0 -------> PC4
 * ETH_MII_RXD1/ETH_RMII_RXD1 -------> PC5
 * ETH_MII_TX_EN/ETH_RMII_TX_EN -----> PG11
 * ETH_MII_TXD0/ETH_RMII_TXD0 -------> PG13
 * ETH_MII_TXD1/ETH_RMII_TXD1 -------> PG14
 * ETH_MII_CRS ----------------------> PH2
 * ETH_MII_COL ----------------------> PH3
 * ETH_MII_RXD2 ---------------------> PH6
 * ETH_MII_RXD3 ---------------------> PH7
 * ETH_MII_RX_ER --------------------> PI10
 */
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static struct stm32f2_gpio_dsc mac_gpio[] = {
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	{STM32F2_GPIO_PORT_A, 1},
	{STM32F2_GPIO_PORT_A, 2},
	{STM32F2_GPIO_PORT_A, 7},

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#ifndef CONFIG_STM32_ETH_RMII
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	{STM32F2_GPIO_PORT_B, 5},
	{STM32F2_GPIO_PORT_B, 8},
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#endif
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	{STM32F2_GPIO_PORT_C, 1},
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#ifndef CONFIG_STM32_ETH_RMII
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	{STM32F2_GPIO_PORT_C, 2},
	{STM32F2_GPIO_PORT_C, 3},
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#endif
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	{STM32F2_GPIO_PORT_C, 4},
	{STM32F2_GPIO_PORT_C, 5},

	{STM32F2_GPIO_PORT_G, 11},
	{STM32F2_GPIO_PORT_G, 13},
	{STM32F2_GPIO_PORT_G, 14},

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#ifndef CONFIG_STM32_ETH_RMII
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	{STM32F2_GPIO_PORT_H, 2},
	{STM32F2_GPIO_PORT_H, 3},
	{STM32F2_GPIO_PORT_H, 6},
	{STM32F2_GPIO_PORT_H, 7},

	{STM32F2_GPIO_PORT_I, 10}
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#endif
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};

/*
 * Prototypes
 */
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static  s32 stm_eth_init(struct eth_device *dev, bd_t *bd);
static  s32 stm_eth_send(struct eth_device *dev, volatile void *pkt, s32 len);
static  s32 stm_eth_recv(struct eth_device *dev);
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static void stm_eth_halt(struct eth_device *dev);

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static  s32 stm_phy_write(struct stm_eth_dev *mac, u16 reg, u16 val);
static  s32 stm_phy_read(struct stm_eth_dev *mac, u16 reg, u16 *val);
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/*
 * Initialize driver
 */
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s32 stm32_eth_init(bd_t *bd)
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{
	struct stm_eth_dev	*mac;
	struct eth_device	*netdev;
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	s32			rv;
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	u32			val;
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	mac = malloc(sizeof(struct stm_eth_dev));
	if (!mac) {
		printf("Error: failed to allocate %dB of memory for %s\n",
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			sizeof(struct stm_eth_dev), STM32_MAC_NAME);
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		rv = -ENOMEM;
		goto out;
	}
	memset(mac, 0, sizeof(struct stm_eth_dev));

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	/*
	 * Enable SYSCFG clock
	 */
	STM32_RCC->apb2enr |= STM32_RXX_ENR_SYSCFG;

	/*
	 * Set MII mode
	 */
	val = STM32_SYSCFG->pmc;
	val &= STM32_SYSCFG_PMC_SEL_MSK << STM32_SYSCFG_PMC_SEL_BIT;
#ifndef CONFIG_STM32_ETH_RMII
	val |= STM32_SYSCFG_PMC_SEL_MII << STM32_SYSCFG_PMC_SEL_BIT;
#else
	val |= STM32_SYSCFG_PMC_SEL_RMII << STM32_SYSCFG_PMC_SEL_BIT;
#endif
	STM32_SYSCFG->pmc = val;

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	netdev = &mac->netdev;

	/*
	 * Map registers
	 */
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	netdev->iobase = STM32_MAC_BASE;
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	/*
	 * Autodetect PHY
	 */
	mac->phy_adr = 0;
	mac->phy_id  = 0xFF;

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	sprintf(netdev->name, STM32_MAC_NAME);
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	netdev->init = stm_eth_init;
	netdev->halt = stm_eth_halt;
	netdev->send = stm_eth_send;
	netdev->recv = stm_eth_recv;

	rv = eth_register(netdev);
out:
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	if (rv != 0 && mac)
		free(mac);

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	return rv;
}

/*
 * Initialize PHY
 */
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static s32 stm_phy_init(struct stm_eth_dev *mac)
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{
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	s32	i, rv;
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	u16	val;

	/*
	 * Check if we already inited
	 */
	if (mac->phy_id != 0xFF)
		goto ok;

	/*
	 * Probe (find) a PHY
	 */
	for (i = 0; i < 32; i++) {
		mac->phy_adr = i;
		rv = stm_phy_read(mac, PHY_PHYIDR1, &val);
		if (rv != 0 || val == 0xFFFF || val == 0)
			continue;

		mac->phy_id = (val & 0xFFFF) << 16;
		rv = stm_phy_read(mac, PHY_PHYIDR2, &val);
		if (rv == 0 && val != 0xFFFF && val != 0)
			mac->phy_id |= val & 0xFFFF;
		break;
	}
	if (i == 32) {
		mac->phy_id = 0xFF;
		printf("%s: PHY not found.\n", __func__);
		rv = -ENODEV;
		goto out;
	}

ok:
	debug("%s: found PHY id = %#x at addr %#x\n", __func__,
	      mac->phy_id, mac->phy_adr);
	rv = 0;
out:
	return rv;
}

/*
 * Get link status
 */
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static s32 stm_phy_link_get(struct stm_eth_dev *mac,
			    s32 *link_up, s32 *full_dup, s32 *speed)
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{
	u16	val;
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	s32	rv;
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	rv = stm_phy_read(mac, PHY_BMSR, &val);
	if (rv != 0)
		goto out;
	*link_up  = (val & PHY_BMSR_LS) ? 1 : 0;

	rv = stm_phy_read(mac, PHY_BMCR, &val);
	if (rv != 0)
		goto out;
	*full_dup = (val & PHY_BMSR_EXT_STAT) ? 1 : 0;
	*speed    = (val & (PHY_BMSR_100TXH | PHY_BMSR_100TXF)) ? 100 : 10;

	rv = 0;
out:
	return rv;
}

/*
 * Setup link status
 */
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static s32 stm_phy_link_setup(struct stm_eth_dev *mac)
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{
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	static s32	link_inited;
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	s32		link_up, full_dup, speed, rv, timeout;
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	u32		cr_val;
	u16		val;

	/*
	 * Get link status
	 */
	rv = stm_phy_link_get(mac, &link_up, &full_dup, &speed);
	if (rv != 0)
		goto out;

	/*
	 * Force auto-negotiation procedure on each U-Boot start. If
	 * CPU had been reseted (with 'RESET' button), but PHY didn't,
	 * then because of GPIO reinitialization - the sync with PHY may
	 * be lost, and the very first frame sent to PHY will be lost as
	 * well. Autonegotiation procedure fixes this, so at very first
	 * time after start we force it.
	 */
	if (link_up && link_inited)
		goto link_set;

	/*
	 * Enable auto-negotiation
	 */
	printf("Auto-negotiation...");
	rv = stm_phy_read(mac, PHY_BMCR, &val);
	if (rv != 0)
		goto out;
	rv = stm_phy_write(mac, PHY_BMCR,
			   val | PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
	if (rv != 0)
		goto out;

	/*
	 * Wait until auto-negotioation complete
	 */
550
551
552
553
554
555
556
	timeout = STM32_PHY_AUTONEG_TIMEOUT;
	while (timeout-- > 0) {
		if (stm_phy_read(mac, PHY_BMSR, &val) == 0 &&
		    (val & PHY_BMSR_AUTN_COMP))
			timeout = 0;
		else
			udelay(100);
557
	}
558
559
560
	if (val & PHY_BMSR_AUTN_COMP)
		printf("completed.\n");
	else
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
		printf("timeout.\n");

	/*
	 * Get link status
	 */
	rv = stm_phy_link_get(mac, &link_up, &full_dup, &speed);
	if (rv != 0)
		goto out;
	if (!link_up) {
		printf("Link is DOWN.\n");
		rv = -ENETUNREACH;
		goto out;
	}

link_set:
576
	cr_val = STM32_MAC->maccr;
577
578
579
	printf("%s: link UP ", mac->netdev.name);
	if (speed == 100) {
		printf("(100/");
580
		cr_val |= STM32_MAC_CR_FES;
581
582
	} else {
		printf("(10/");
583
		cr_val &= ~STM32_MAC_CR_FES;
584
585
586
587
	}

	if (full_dup) {
		printf("Full)\n");
588
		cr_val |= STM32_MAC_CR_DM;
589
590
	} else {
		printf("Half)\n");
591
		cr_val &= ~STM32_MAC_CR_DM;
592
	}
593
	STM32_MAC->maccr = cr_val;
594
595
596
597
598
599
600

	link_inited = 1;
	rv = 0;
out:
	return rv;
}

601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
/*
 * Helper function used in stm_phy_read() and stm_phy_write()
 */
static int stm_phy_wait_busy(int timeout)
{
	int rv;

	rv = -ETIMEDOUT;
	while (timeout-- > 0) {
		if (STM32_MAC->macmiiar & STM32_MAC_MIIAR_MB) {
			udelay(100);
		} else {
			timeout = 0;
			rv = 0;
		}
	}

	if (rv != 0)
		printf("%s: timed out\n", __func__);

	return rv;
}

624
625
626
/*
 * Write PHY
 */
627
static s32 stm_phy_write(struct stm_eth_dev *mac, u16 reg, u16 val)
628
629
630
{
	u16	adr = mac->phy_adr;
	u32	tmp;
631
	s32	rv;
632

633
	if (stm_phy_wait_busy(STM32_PHY_WRITE_TIMEOUT) != 0) {
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
		/*
		 * MII is busy
		 */
		rv = -EBUSY;
		goto out;
	}

	/*
	 * Prepare MII register address value:
	 * - keep CR;
	 * - set PHY device address
	 * - set PHY register address
	 * - set write mode
	 * - set MII Busy
	 */
649
650
	tmp = STM32_MAC->macmiiar;
	tmp &= STM32_MAC_MIIAR_CR_MSK << STM32_MAC_MIIAR_CR_BIT;
651

652
653
	adr &= STM32_MAC_MIIAR_PA_MSK;
	tmp |= adr << STM32_MAC_MIIAR_PA_BIT;
654

655
656
	reg &= STM32_MAC_MIIAR_MR_MSK;
	tmp |= reg << STM32_MAC_MIIAR_MR_BIT;
657

658
	tmp |= STM32_MAC_MIIAR_MW | STM32_MAC_MIIAR_MB;
659
660
661
662

	/*
	 * Write to regs, and wait for completion
	 */
663
664
	STM32_MAC->macmiidr = val;
	STM32_MAC->macmiiar = tmp;
665

666
	if (stm_phy_wait_busy(STM32_PHY_WRITE_TIMEOUT) != 0) {
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
		/*
		 * Transaction failed: Write timeout
		 */
		rv = -ETIMEDOUT;
		goto out;
	}

	/*
	 * Transaction OK
	 */
	rv = 0;
out:
	return rv;
}

/*
 * Read PHY
 */
685
static s32 stm_phy_read(struct stm_eth_dev *mac, u16 reg, u16 *val)
686
687
688
{
	u16	adr = mac->phy_adr;
	u32	tmp;
689
	s32	rv;
690

691
	if (stm_phy_wait_busy(STM32_PHY_READ_TIMEOUT) != 0) {
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
		/*
		 * MII is busy
		 */
		rv = -EBUSY;
		goto out;
	}

	/*
	 * Prepare MII register address value:
	 * - keep CR;
	 * - set PHY device address
	 * - set PHY register address
	 * - set read mode
	 * - set MII Busy
	 */
707
708
	tmp = STM32_MAC->macmiiar;
	tmp &= STM32_MAC_MIIAR_CR_MSK << STM32_MAC_MIIAR_CR_BIT;
709

710
711
	adr &= STM32_MAC_MIIAR_PA_MSK;
	tmp |= adr << STM32_MAC_MIIAR_PA_BIT;
712

713
714
	reg &= STM32_MAC_MIIAR_MR_MSK;
	tmp |= reg << STM32_MAC_MIIAR_MR_BIT;
715

716
	tmp |= STM32_MAC_MIIAR_MB;
717
718
719
720

	/*
	 * Write to reg, and wait for completion
	 */
721
	STM32_MAC->macmiiar  = tmp;
722

723
	if (stm_phy_wait_busy(STM32_PHY_READ_TIMEOUT) != 0) {
724
725
726
727
728
729
730
731
732
733
		/*
		 * Transaction failed: read timeout
		 */
		rv = -ETIMEDOUT;
		goto out;
	}

	/*
	 * Transaction OK
	 */
734
	*val = STM32_MAC->macmiidr;
735
736
737
738
739
740
741

	rv = 0;
out:
	return rv;
}

/*
742
 * Init STM32 MAC buffer descriptors
743
744
745
 */
static void stm_mac_bd_init(struct stm_eth_dev *mac)
{
746
	s32	i;
747
748
749
750

	/*
	 * Init Tx buffer descriptor
	 */
751
	mac->tx_bd.stat = STM32_DMA_TBD_TCH;
752
753
754
755
756
757
758
759
	mac->tx_bd.ctrl = 0;
	mac->tx_bd.buf  = NULL;
	mac->tx_bd.next = &mac->tx_bd;

	/*
	 * Init Rx buffer descriptors
	 */
	for (i = 0; i < PKTBUFSRX; i++) {
760
		mac->rx_bd[i].stat = STM32_DMA_RBD_DMA_OWN;
761
		mac->rx_bd[i].ctrl = STM32_DMA_RBD_RCH | PKTSIZE_ALIGN;
762
763
764
765
766
767
768
769
770
771
772
773
		mac->rx_bd[i].buf  = &mac->rx_buf[i][0];
		mac->rx_bd[i].next = &mac->rx_bd[(i + 1) % PKTBUFSRX];
	}

	/*
	 * Set our internal rx bd pointer to start
	 */
	mac->rx_bd_idx = 0;

	/*
	 * Program DMA with the addresses of descriptor chains
	 */
774
775
	STM32_MAC->dmatdlar = (u32)&mac->tx_bd;
	STM32_MAC->dmardlar = (u32)&mac->rx_bd[0];
776
777
778
779
780
781
782
783
784
785
786
787
788
789
}

/*
 * Set MAC address
 */
static void stm_mac_address_set(struct stm_eth_dev *mac)
{
	struct eth_device	*netdev = &mac->netdev;

	debug("%s: mac is %#x:%#x:%#x:%#x:%#x:%#x.\n", __func__,
	      netdev->enetaddr[0], netdev->enetaddr[1],
	      netdev->enetaddr[2], netdev->enetaddr[3],
	      netdev->enetaddr[4], netdev->enetaddr[5]);

790
	STM32_MAC->maca0hr = (netdev->enetaddr[5] <<  8) |
791
			     (netdev->enetaddr[4] <<  0);
792
	STM32_MAC->maca0lr = (netdev->enetaddr[3] << 24) |
793
794
795
			     (netdev->enetaddr[2] << 16) |
			     (netdev->enetaddr[1] <<  8) |
			     (netdev->enetaddr[0] <<  0);
796
797
798
799
800
}

/*
 * Init GPIOs used by MAC
 */
801
static s32 stm_mac_gpio_init(struct stm_eth_dev *mac)
802
{
803
	static s32	gpio_inited;
804

805
	s32		i, rv;
806
807
808
809
810
811
812
813
814

	/*
	 * Init GPIOs only once at start. Otherwise, reiniting then on
	 * each halt/init call from u-boot Net subsystem we may loose
	 * the very first frame sending to net: MAC in this case reports
	 * that frame had been successfully sent, but there is no frame
	 * on wires. Probably, some synchronization with PHY is lost if
	 * we do this GPIO re-initialization.
	 */
815
816
	if (gpio_inited) {
		rv = 0;
817
		goto out;
818
	}
819
820
821
822
823

	/*
	 * Set GPIOs Alternative function
	 */
	for (i = 0; i < sizeof(mac_gpio)/sizeof(mac_gpio[0]); i++) {
824
825
826
827
		rv = stm32f2_gpio_config(&mac_gpio[i],
					 STM32F2_GPIO_ROLE_ETHERNET);
		if (rv != 0)
			goto out;
828
829
830
	}

	gpio_inited = 1;
831
	rv = 0;
832
out:
833
	return rv;
834
835
836
}

/*
837
 * Init STM32 MAC hardware
838
 */
839
static s32 stm_mac_hw_init(struct stm_eth_dev *mac)
840
841
{
	u32	tmp, hclk;
842
	s32	rv, timeout;
843
844
845
846

	/*
	 * Init GPIOs
	 */
847
848
849
	rv = stm_mac_gpio_init(mac);
	if (rv != 0)
		goto out;
850
851
852
853

	/*
	 * Enable Ethernet clocks
	 */
854
	STM32_RCC->ahb1enr |= STM32_RCC_ENR_ETHMACEN   |
855
856
			      STM32_RCC_ENR_ETHMACTXEN |
			      STM32_RCC_ENR_ETHMACRXEN;
857
858
859
860

	/*
	 * Reset all MAC subsystem internal regs and logic
	 */
861
862
	STM32_RCC->ahb1rstr |= STM32_RCC_AHB1RSTR_MAC;
	STM32_RCC->ahb1rstr &= ~STM32_RCC_AHB1RSTR_MAC;
863

864
	STM32_MAC->dmabmr |= STM32_MAC_DMABMR_SR;
865
866
867
868
869
870
871
872
873
874

	timeout = STM32_MAC_INIT_TIMEOUT;
	rv = -EBUSY;
	while (timeout-- > 0) {
		if (STM32_MAC->dmabmr & STM32_MAC_DMABMR_SR) {
			udelay(100);
		} else {
			timeout = 0;
			rv = 0;
		}
875
	}
876
	if (rv != 0) {
877
878
879
880
881
882
883
884
885
886
887
		printf("%s: failed reset MAC subsystem.\n", __func__);
		goto out;
	}

	/*
	 * Configure DMA:
	 * - address aligned beats (32-bit aligned src & dst addresses),
	 * - fixed burst, and 32 beat max burst lengths,
	 * - round-robin DMA arbitration Rx:Tx<->2:1;
	 * - enable use of separate PBL for Rx and Tx.
	 */
888
	STM32_MAC->dmabmr = (32 << STM32_MAC_DMABMR_PBL_BIT) |
889
890
891
892
893
			    (32 << STM32_MAC_DMABMR_RDP_BIT) |
			    (STM32_MAC_DMABMR_RTPR_2_1 <<
			     STM32_MAC_DMABMR_RTPR_BIT) |
			    STM32_MAC_DMABMR_FB | STM32_MAC_DMABMR_USP |
			    STM32_MAC_DMABMR_AAB;
894
895
896
897
898
899
900

	/*
	 * Configure Ethernet CSR Clock Range
	 */
	hclk = clock_get(CLOCK_HCLK);
	if (hclk >= 20000000 && hclk < 35000000) {
		/* CSR Clock range between 20-35 MHz */
901
		tmp = STM32_MAC_MIIAR_CR_DIV16 << STM32_MAC_MIIAR_CR_BIT;
902
903
	} else if (hclk >= 35000000 && hclk < 60000000) {
		/* CSR Clock range between 35-60 MHz */
904
		tmp = STM32_MAC_MIIAR_CR_DIV26 << STM32_MAC_MIIAR_CR_BIT;
905
906
	} else if (hclk >= 60000000 && hclk < 100000000) {
		/* CSR Clock range between 60-100 MHz */
907
		tmp = STM32_MAC_MIIAR_CR_DIV42 << STM32_MAC_MIIAR_CR_BIT;
908
	} else {
909
		/* CSR Clock range between 100-168 MHz */
910
		tmp = STM32_MAC_MIIAR_CR_DIV62 << STM32_MAC_MIIAR_CR_BIT;
911
912
	}

913
914
915
916
917
918
	if (stm_phy_wait_busy(STM32_PHY_READ_TIMEOUT) != 0) {
		/*
		 * MII is busy
		 */
		rv = -EBUSY;
		goto out;
919
	}
920
	STM32_MAC->macmiiar = tmp;
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939

	/*
	 * Init PHY
	 */
	rv = stm_phy_init(mac);
	if (rv != 0)
		goto out;

	/*
	 * Setup link, and complete MAC initialization
	 */
	rv = stm_phy_link_setup(mac);
	if (rv != 0)
		goto out;
out:
	return rv;
}

/*
940
 * Init STM32 MAC and DMA
941
 */
942
static s32 stm_eth_init(struct eth_device *dev, bd_t *bd)
943
944
{
	struct stm_eth_dev	*mac = to_stm_eth(dev);
945
	s32			rv;
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966

	/*
	 * Init hw
	 */
	rv = stm_mac_hw_init(mac);
	if (rv != 0)
		goto out;

	/*
	 * Set MAC address
	 */
	stm_mac_address_set(mac);

	/*
	 * Init buffer descriptors
	 */
	stm_mac_bd_init(mac);

	/*
	 * Enable TX
	 */
967
	STM32_MAC->maccr |= STM32_MAC_CR_TE;
968
969
970
971

	/*
	 * Flush Transmit FIFO
	 */
972
973
	STM32_MAC->dmaomr |= STM32_MAC_DMAOMR_FTF;
	while (STM32_MAC->dmaomr & STM32_MAC_DMAOMR_FTF);
974
975
976
977

	/*
	 * Enable RX
	 */
978
	STM32_MAC->maccr |= STM32_MAC_CR_RE;
979
980
981
982

	/*
	 * Start DMA TX and RX
	 */
983
984
	STM32_MAC->dmaomr |= STM32_MAC_DMAOMR_ST;
	STM32_MAC->dmaomr |= STM32_MAC_DMAOMR_SR;
985
986
987
988
989
990
991
992
993
out:
	if (rv != 0)
		printf("%s: failed (%d).\n", __func__, rv);
	return rv;
}

/*
 * Send frame
 */
994
static s32 stm_eth_send(struct eth_device *dev, volatile void *pkt, s32 len)
995
996
{
	struct stm_eth_dev	*mac = to_stm_eth(dev);
997
	s32			rv, tout;
998
999
1000
1001
1002
1003
1004
1005
1006
1007

	if (len > PKTSIZE_ALIGN) {
		printf("%s: frame too long (%d).\n", __func__, len);
		rv = -EINVAL;
		goto out;
	}

	/*
	 * Make sure nothing is txing now
	 */
1008
	if (mac->tx_bd.stat & STM32_DMA_TBD_DMA_OWN) {
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
		printf("%s: busy.\n", __func__);
		rv = -EBUSY;
		goto out;
	}

	/*
	 * Set up BD
	 */
	mac->tx_bd.buf   = pkt;
	mac->tx_bd.ctrl  = len;
1019
1020
	mac->tx_bd.stat |= STM32_DMA_TBD_FS | STM32_DMA_TBD_LS |
			   STM32_DMA_TBD_DMA_OWN;
1021
1022
1023
1024

	/*
	 * If Tx buffer unavailable flag is set, then clear it and resume
	 */
1025
1026
1027
	if (STM32_MAC->dmasr & STM32_MAC_DMASR_TBUS) {
		STM32_MAC->dmasr &= ~STM32_MAC_DMASR_TBUS;
		STM32_MAC->dmatpdr = 0;
1028
1029
1030
1031
1032
	}

	/*
	 * Wait until transmit completes
	 */
1033
1034
1035
	tout = STM32_MAC_TX_TIMEOUT;
	rv = -ETIMEDOUT;
	while (tout-- > 0) {
1036
		if (mac->tx_bd.stat & STM32_DMA_TBD_DMA_OWN)
1037
1038
1039
1040
1041
			udelay(1);
		else {
			tout = 0;
			rv = 0;
		}
1042
	}
1043
	if (rv != 0) {
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
		printf("%s: timeout.\n", __func__);
		goto out;
	}

	/*
	 * Tx done.
	 */
	rv = 0;
out:
	return rv;
}

/*
 * Process received frames (if any)
 */
1059
static s32 stm_eth_recv(struct eth_device *dev)
1060
1061
1062
1063
1064
1065
1066
1067
1068
{
	volatile struct stm_eth_dma_bd	*bd;
	struct stm_eth_dev		*mac = to_stm_eth(dev);
	u32				len;

	/*
	 * Walk through the list of rx bds and process rxed frames until
	 * detect BD owned by DMA
	 */
1069
	while (!(mac->rx_bd[mac->rx_bd_idx].stat & STM32_DMA_RBD_DMA_OWN)) {
1070
1071
1072
1073
1074
1075
1076
		bd = &mac->rx_bd[mac->rx_bd_idx];

		/*
		 * RX buf size we use should be enough for storing the whole
		 * ethernet frame with checksum (1518), so the following
		 * shouldn't happen
		 */
1077
1078
		if ((bd->stat & (STM32_DMA_RBD_FS | STM32_DMA_RBD_LS)) !=
		    (STM32_DMA_RBD_FS | STM32_DMA_RBD_LS)) {
1079
1080
1081
1082
1083
1084
1085
			printf("%s: warn, frame split (0x%08x).\n", __func__,
				bd->stat);
		}

		/*
		 * Get length, and take 4 CRC bytes into account
		 */
1086
1087
		len  = (bd->stat >> STM32_DMA_RBD_FL_BIT) &
		       STM32_DMA_RBD_FL_MSK;
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
		len -= 4;

		/*
		 * Pass frame upper
		 */
		NetReceive(bd->buf, len);

		/*
		 * Mark BD as ready for rx again, and switch to the next BD
		 */
1098
		bd->stat = STM32_DMA_RBD_DMA_OWN;
1099
1100
1101
1102
1103
1104
		mac->rx_bd_idx = (mac->rx_bd_idx + 1) % PKTBUFSRX;

		/*
		 * If rx buf unavailable flag is set, clear it and resume
		 * reception
		 */
1105
		if (STM32_MAC->dmasr & STM32_MAC_DMASR_RBUS) {
1106
1107
1108
1109
			/*
			 * This is actually overflow, frame(s) lost
			 */
			printf("%s: RX overflow.\n", __func__);
1110
1111
			STM32_MAC->dmasr &= ~STM32_MAC_DMASR_RBUS;
			STM32_MAC->dmarpdr = 0;
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
		}
	}

	return 0;
}

/*
 * Halt MAC
 */
static void stm_eth_halt(struct eth_device *dev)
{
	/*
	 * Stop DMA, and disable receiver and transmitter
	 */
1126
1127
	STM32_MAC->dmaomr &= ~(STM32_MAC_DMAOMR_ST | STM32_MAC_DMAOMR_SR);
	STM32_MAC->maccr  &= ~(STM32_MAC_CR_TE | STM32_MAC_CR_RE);
1128
}