stm32_eth.c 27.3 KB
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/*
 * (C) Copyright 2011
 *
 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * STM32 F2 Ethernet driver
 */

#include <config.h>

/*
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 * Define DEBUG to enable debug() messages in this module
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 */
#undef DEBUG

#include <common.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include <asm/errno.h>

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#include <asm/arch/stm32.h>
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#include <asm/arch/stm32f2_gpio.h>

#if defined(CONFIG_STM32F2_SYS_CLK_HSI)
# error "Can't run MAC with this CLK configuration."
#endif

/*
 * Device name
 */
#define STM32F2_MAC_NAME		"STM32F2_MAC"

/*
 * STM32F2 MAC/DMA definitions
 */
/*
 * MAC registers base
 */
#define STM32F2_MAC_BASE		(STM32F2_AHB1PERITH_BASE + 0x8000)

/*
 * MACCR reg fields
 */
#define STM32F2_MAC_CR_RE		(1 << 2)	/* Received enable    */
#define STM32F2_MAC_CR_TE		(1 << 3)	/* Transmitter enable */
#define STM32F2_MAC_CR_DM		(1 << 11)	/* Duplex mode	      */
#define STM32F2_MAC_CR_FES		(1 << 14)	/* Fast Eth speed     */

/*
 * MACMIIAR reg fields
 */
#define STM32F2_MAC_MIIAR_MB		(1 << 0)	/* MII busy	      */
#define STM32F2_MAC_MIIAR_MW		(1 << 1)	/* MII write	      */

#define STM32F2_MAC_MIIAR_CR_BIT	2		/* Clock range	      */
#define STM32F2_MAC_MIIAR_CR_MSK	0x7
#define STM32F2_MAC_MIIAR_CR_DIV42	0x0		/* 60-100 MHz	      */
#define STM32F2_MAC_MIIAR_CR_DIV62	0x1		/* 100-120 MHz	      */
#define STM32F2_MAC_MIIAR_CR_DIV16	0x2		/* 20-35 MHz	      */
#define STM32F2_MAC_MIIAR_CR_DIV26	0x3		/* 35-60 MHz	      */

#define STM32F2_MAC_MIIAR_MR_BIT	6		/* MII register	      */
#define STM32F2_MAC_MIIAR_MR_MSK	0x1F

#define STM32F2_MAC_MIIAR_PA_BIT	11		/* PHY address	      */
#define STM32F2_MAC_MIIAR_PA_MSK	0x1F

/*
 * DMABMR reg fields
 */
#define STM32F2_MAC_DMABMR_SR		(1 << 0)	/* Software reset     */

#define STM32F2_MAC_DMABMR_PBL_BIT	8		/* Burst length	      */
#define STM32F2_MAC_DMABMR_PBL_MSK	0x3F

#define STM32F2_MAC_DMABMR_RTPR_BIT	14		/* Rx:Tx priority rat.*/
#define STM32F2_MAC_DMABMR_RTPR_MSK	0x3
#define STM32F2_MAC_DMABMR_RTPR_1_1	0x0		/* 1 : 1	      */
#define STM32F2_MAC_DMABMR_RTPR_2_1	0x1		/* 2 : 1	      */
#define STM32F2_MAC_DMABMR_RTPR_3_1	0x2		/* 3 : 1	      */
#define STM32F2_MAC_DMABMR_RTPR_4_1	0x3		/* 4 : 1	      */

#define STM32F2_MAC_DMABMR_FB		(1 << 16)	/* Fixed burst	      */

#define STM32F2_MAC_DMABMR_RDP_BIT	17		/* RX DMA PBL	      */
#define STM32F2_MAC_DMABMR_RDP_MSK	0x3F

#define STM32F2_MAC_DMABMR_USP		(1 << 23)	/* Use separate PBL   */
#define STM32F2_MAC_DMABMR_AAB		(1 << 25)	/* Adr-aligned beats  */

/*
 * DMASR reg fields
 */
#define STM32F2_MAC_DMASR_TBUS		(1 << 2)	/* Tx buf unavailable */
#define STM32F2_MAC_DMASR_RBUS		(1 << 7)	/* Rx buf unavailable */

/*
 * DMAOMR reg fields
 */
#define STM32F2_MAC_DMAOMR_SR		(1 << 1)	/* Start/stop rx      */
#define STM32F2_MAC_DMAOMR_ST		(1 << 13)	/* Start/stop tx      */
#define STM32F2_MAC_DMAOMR_FTF		(1 << 20)	/* Flush tx FIFO      */

/*
 * DMA transmit buffer descriptor bits
 */
#define STM32F2_DMA_TBD_DMA_OWN		(1 << 31)	/* DMA/CPU owns bd    */
#define STM32F2_DMA_TBD_LS		(1 << 29)	/* Last segment	      */
#define STM32F2_DMA_TBD_FS		(1 << 28)	/* First segment      */
#define STM32F2_DMA_TBD_TCH		(1 << 20)	/* 2nd address chained*/

/*
 * DMA receive buffer descriptor bits
 */
#define STM32F2_DMA_RBD_DMA_OWN		(1 << 31)	/* DMA/CPU owns bd    */
#define STM32F2_DMA_RBD_FL_BIT		16		/* Frame length	      */
#define STM32F2_DMA_RBD_FL_MSK		0x3FFF
#define STM32F2_DMA_RBD_FS		(1 << 9)	/* First descriptor   */
#define STM32F2_DMA_RBD_LS		(1 << 8)	/* Last descriptor    */

#define STM32F2_DMA_RBD_RCH		(1 << 14)	/* 2nd address chained*/

/*
 * STM32F2 SYSCFG definitions
 */
#define STM32F2_SYSCFG_BASE		(STM32F2_APB2PERITH_BASE + 0x3800)

/*
 * PMC reg fields
 */
#define STM32F2_SYSCFG_PMC_SEL_BIT	23		/* MII/RMII selection */
#define STM32F2_SYSCFG_PMC_SEL_MSK	0x1

#define STM32F2_SYSCFG_PMC_SEL_MII	0
#define STM32F2_SYSCFG_PMC_SEL_RMII	1

/*
 * STM32F2 RCC MAC specific definitions
 */
#define STM32F2_RCC_CFGR_MCO1_BIT	21		/* MC clock output 1  */
#define STM32F2_RCC_CFGR_MCO1_MSK	0x3

#define STM32F2_RCC_CFGR_MCO1_HSI	0x0		/* Clock source	      */
#define STM32F2_RCC_CFGR_MCO1_LSE	0x1
#define STM32F2_RCC_CFGR_MCO1_HSE	0x2
#define STM32F2_RCC_CFGR_MCO1_PLL	0x3

#define STM32F2_RCC_CFGR_MCO1PRE_BIT	24		/* MCO1 prescaler     */
#define STM32F2_RCC_CFGR_MCO1PRE_MSK	0x7

#define STM32F2_RCC_CFGR_MCO1PRE_DIVNO	0x0		/* Division by X      */
#define STM32F2_RCC_CFGR_MCO1PRE_DIV2	0x4
#define STM32F2_RCC_CFGR_MCO1PRE_DIV3	0x5
#define STM32F2_RCC_CFGR_MCO1PRE_DIV4	0x6
#define STM32F2_RCC_CFGR_MCO1PRE_DIV5	0x7

#define STM32F2_RCC_AHB1RSTR_MAC	(1 << 25)	/* Reset MAC	      */

#define STM32F2_RXX_ENR_SYSCFG		(1 << 14)	/* SYSCFG clock	      */

#define STM32F2_RCC_ENR_ETHMACEN	(1 << 25)	/* Ethernet MAC clock */
#define STM32F2_RCC_ENR_ETHMACTXEN	(1 << 26)	/* Ethernet Tx clock  */
#define STM32F2_RCC_ENR_ETHMACRXEN	(1 << 27)	/* Ethernet Rx clock  */

/*
 * Different timeouts (in cycles)
 * FIXME: replace this stuff with us/ms timeouts (when implement timer support)
 */
#define STM32F2_PHY_READ_TIMEOUT	0x4FFFF
#define STM32F2_PHY_WRITE_TIMEOUT	0x4FFFF
#define STM32F2_PHY_AUTONEG_TIMEOUT	0x10000

#define STM32F2_MAC_TX_TIMEOUT		0xFFFFFF
#define STM32F2_MAC_INIT_TIMEOUT	0xFFFFFF

/*
 * MAC, MMC, PTP, DMA register map
 */
struct stm32f2_mac_regs {
	u32	maccr;		/* MAC configuration			      */
	u32	macffr;		/* MAC frame filter			      */
	u32	machthr;	/* MAC hash table high			      */
	u32	machtlr;	/* MAC hash table low			      */
	u32	macmiiar;	/* MAC MII address			      */
	u32	macmiidr;	/* MAC MII data				      */
	u32	macfcr;		/* MAC flow control			      */
	u32	macvlantr;	/* MAC VLAN tag				      */
	u32	rsv0[2];
	u32	macrwuffr;	/* MAC remote wakeup frame filter	      */
	u32	macpmtcsr;	/* MAC PMT control and status		      */
	u32	rsv1;
	u32	macdbgr;	/* MAC debug				      */
	u32	macsr;		/* MAC interrupt status			      */
	u32	macimr;		/* MAC interrupt mask			      */
	u32	maca0hr;	/* MAC address 0 high			      */
	u32	maca0lr;	/* MAC address 0 low			      */
	u32	maca1hr;	/* MAC address 1 high			      */
	u32	maca1lr;	/* MAC address 1 low			      */
	u32	maca2hr;	/* MAC address 2 high			      */
	u32	maca2lr;	/* MAC address 2 low			      */
	u32	maca3hr;	/* MAC address 3 high			      */
	u32	maca3lr;	/* MAC address 3 low			      */
	u32	rsv2[40];
	u32	mmccr;		/* MMC control				      */
	u32	mmcrir;		/* MMC receive interrupt		      */
	u32	mmctir;		/* MMC transmit interrupt		      */
	u32	mmcrimr;	/* MMC receive interrupt mask		      */
	u32	mmctimr;	/* MMC transmit interrupt mask		      */
	u32	rsv3[14];
	u32	mmctgfsccr;	/* MMC transmitted good frms after single col */
	u32	mmctgfmsccr;	/* MMC transmitted good frms after more col   */
	u32	rsv4[5];
	u32	mmctgfcr;	/* MMC transmitted good frames counter	      */
	u32	rsv5[10];
	u32	mmcrfcecr;	/* MMC received frames with CRC error counter */
	u32	mmcrfaecr;	/* MMC received frames with alignment error   */
	u32	rsv6[10];
	u32	mmcrgufcr;	/* MMC received good unicast frames counter   */
	u32	rsv7[334];
	u32	ptptscr;	/* PTP time stamp control		      */
	u32	ptpssir;	/* PTP subsecond increment		      */
	u32	ptptshr;	/* PTP time stamp high			      */
	u32	ptptslr;	/* PTP time stamp low			      */
	u32	ptptshur;	/* PTP time stamp high update		      */
	u32	ptptslur;	/* PTP time stamp low update		      */
	u32	ptptsar;	/* PTP time stamp addend		      */
	u32	ptptthr;	/* PTP target time high			      */
	u32	ptpttlr;	/* PTP target time low			      */
	u32	rsv8;
	u32	ptptssr;	/* PTP time stamp status		      */
	u32	ptpppscr;	/* PTP PPS control			      */
	u32	rsv9[564];
	u32	dmabmr;		/* DMA bus mode				      */
	u32	dmatpdr;	/* DMA transmit poll demand		      */
	u32	dmarpdr;	/* DMA receive poll demand		      */
	u32	dmardlar;	/* DMA receive descriptor list address	      */
	u32	dmatdlar;	/* DMA transmit descriptor list address	      */
	u32	dmasr;		/* DMA status				      */
	u32	dmaomr;		/* DMA operation mode			      */
	u32	dmaier;		/* DMA interrupt enable			      */
	u32	dmamfbocr;	/* DMA missed frame and buffer overflow	      */
	u32	dmarswtr;	/* DMA receive status watchdog timer	      */
	u32	rsv10[8];
	u32	dmachtdr;	/* DMA current host transmit descriptor	      */
	u32	dmachrdr;	/* DMA current host receive descriptor	      */
	u32	dmachtbar;	/* DMA current host transmit buffer address   */
	u32	dmachrbar;	/* DMA current host receive buffer address    */
};
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#define STM32F2_MAC	((volatile struct stm32f2_mac_regs *)STM32F2_MAC_BASE)
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/*
 * SYSCFG register map
 */
struct stm32f2_syscfg_regs {
	u32	memrmp;		/* Memory remap				      */
	u32	pmc;		/* Peripheral mode configuration	      */
	u32	exticr[4];	/* External interrupt configuration	      */
	u32	rsv0[2];
	u32	cmpcr;		/* Compensation cell control		      */
};
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#define STM32F2_SYSCFG	((volatile struct stm32f2_syscfg_regs *)	       \
			 STM32F2_SYSCFG_BASE)
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/*
 * STM32F2 ETH Normal DMA buffer descriptors
 */
struct stm_eth_dma_bd {
	volatile u32			stat;	/* Status		      */
	volatile u32			ctrl;	/* Control, and buffer length */
	volatile u8			*buf;	/* Pointer to buffer	      */
	volatile struct stm_eth_dma_bd	*next;	/* Pointer to next BD in chain*/
};

/*
 * STM32F2 ETH device
 */
struct stm_eth_dev {
	/*
	 * Standard ethernet device
	 */
	struct eth_device		netdev;

	/*
	 * PHY settings
	 */
	u32				phy_id;
	u32				phy_adr;

	/*
	 * DMA buffer descriptors, and index of last processed buf:
	 * - have one Tx buffer descriptor;
	 * - have CONFIG_SYS_RX_ETH_BUFFER rx buffer descriptors.
	 */
	volatile struct stm_eth_dma_bd	tx_bd;
	volatile struct stm_eth_dma_bd	rx_bd[PKTBUFSRX];
	int				rx_bd_idx;

	/*
	 * ETH DMAed buffers:
	 * - send requested buffers directly, i.e. have no local storage;
	 * - receive buffers have length of 1536B (> max eth frm len)
	 */
	volatile u8			rx_buf[PKTBUFSRX][PKTSIZE_ALIGN];
};
#define to_stm_eth(_nd)	container_of(_nd, struct stm_eth_dev, netdev)

/*
 * GPIO configuration
 */
struct stm_mac_gpio {
	u32			port;
	u32			pin;
};

/*
 * Ethernet GPIOs:
 *
 * MCO ------------------------------> PA8
 *
 * ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1
 * ETH_MDIO -------------------------> PA2
 * ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7
 * ETH_PPS_OUT ----------------------> PB5
 * ETH_MII_TXD3 ---------------------> PB8
 * ETH_MDC --------------------------> PC1
 * ETH_MII_TXD2 ---------------------> PC2
 * ETH_MII_TX_CLK -------------------> PC3
 * ETH_MII_RXD0/ETH_RMII_RXD0 -------> PC4
 * ETH_MII_RXD1/ETH_RMII_RXD1 -------> PC5
 * ETH_MII_TX_EN/ETH_RMII_TX_EN -----> PG11
 * ETH_MII_TXD0/ETH_RMII_TXD0 -------> PG13
 * ETH_MII_TXD1/ETH_RMII_TXD1 -------> PG14
 * ETH_MII_CRS ----------------------> PH2
 * ETH_MII_COL ----------------------> PH3
 * ETH_MII_RXD2 ---------------------> PH6
 * ETH_MII_RXD3 ---------------------> PH7
 * ETH_MII_RX_ER --------------------> PI10
 */
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static struct stm32f2_gpio_dsc mac_gpio[] = {
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	{0,  1}, {0,  2}, {0,  7},
	{1,  5}, {1,  8},
	{2,  1}, {2,  2}, {2,  3}, {2,  4}, {2,  5},
	{6, 11}, {6, 13}, {6, 14},
	{7,  2}, {7,  3}, {7,  6}, {7,  7},
	{8, 10}
};

/*
 * Prototypes
 */
static  int stm_eth_init(struct eth_device *dev, bd_t *bd);
static  int stm_eth_send(struct eth_device *dev, volatile void *pkt, int len);
static  int stm_eth_recv(struct eth_device *dev);
static void stm_eth_halt(struct eth_device *dev);

static  int stm_phy_write(struct stm_eth_dev *mac, u16 reg, u16 val);
static  int stm_phy_read(struct stm_eth_dev *mac, u16 reg, u16 *val);

/*
 * Initialize driver
 */
int stm32f2_eth_init(bd_t *bd)
{
	struct stm_eth_dev	*mac;
	struct eth_device	*netdev;
	int			rv;

	mac = malloc(sizeof(struct stm_eth_dev));
	if (!mac) {
		printf("Error: failed to allocate %dB of memory for %s\n",
			sizeof(struct stm_eth_dev), STM32F2_MAC_NAME);
		rv = -ENOMEM;
		goto out;
	}
	memset(mac, 0, sizeof(struct stm_eth_dev));

	netdev = &mac->netdev;

	/*
	 * Map registers
	 */
	netdev->iobase = STM32F2_MAC_BASE;

	/*
	 * Autodetect PHY
	 */
	mac->phy_adr = 0;
	mac->phy_id  = 0xFF;

	sprintf(netdev->name, STM32F2_MAC_NAME);

	netdev->init = stm_eth_init;
	netdev->halt = stm_eth_halt;
	netdev->send = stm_eth_send;
	netdev->recv = stm_eth_recv;

	rv = eth_register(netdev);
out:
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	if (rv != 0 && mac)
		free(mac);

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	return rv;
}

/*
 * Initialize PHY
 */
static int stm_phy_init(struct stm_eth_dev *mac)
{
	int	i, rv;
	u16	val;

	/*
	 * Check if we already inited
	 */
	if (mac->phy_id != 0xFF)
		goto ok;

	/*
	 * Probe (find) a PHY
	 */
	for (i = 0; i < 32; i++) {
		mac->phy_adr = i;
		rv = stm_phy_read(mac, PHY_PHYIDR1, &val);
		if (rv != 0 || val == 0xFFFF || val == 0)
			continue;

		mac->phy_id = (val & 0xFFFF) << 16;
		rv = stm_phy_read(mac, PHY_PHYIDR2, &val);
		if (rv == 0 && val != 0xFFFF && val != 0)
			mac->phy_id |= val & 0xFFFF;
		break;
	}
	if (i == 32) {
		mac->phy_id = 0xFF;
		printf("%s: PHY not found.\n", __func__);
		rv = -ENODEV;
		goto out;
	}

ok:
	debug("%s: found PHY id = %#x at addr %#x\n", __func__,
	      mac->phy_id, mac->phy_adr);
	rv = 0;
out:
	return rv;
}

/*
 * Get link status
 */
static int stm_phy_link_get(struct stm_eth_dev *mac,
			    int *link_up, int *full_dup, int *speed)
{
	u16	val;
	int	rv;

	rv = stm_phy_read(mac, PHY_BMSR, &val);
	if (rv != 0)
		goto out;
	*link_up  = (val & PHY_BMSR_LS) ? 1 : 0;

	rv = stm_phy_read(mac, PHY_BMCR, &val);
	if (rv != 0)
		goto out;
	*full_dup = (val & PHY_BMSR_EXT_STAT) ? 1 : 0;
	*speed    = (val & (PHY_BMSR_100TXH | PHY_BMSR_100TXF)) ? 100 : 10;

	rv = 0;
out:
	return rv;
}

/*
 * Setup link status
 */
static int stm_phy_link_setup(struct stm_eth_dev *mac)
{
	static int	link_inited;

	int		link_up, full_dup, speed, rv, i;
	u32		cr_val;
	u16		val;

	/*
	 * Get link status
	 */
	rv = stm_phy_link_get(mac, &link_up, &full_dup, &speed);
	if (rv != 0)
		goto out;

	/*
	 * Force auto-negotiation procedure on each U-Boot start. If
	 * CPU had been reseted (with 'RESET' button), but PHY didn't,
	 * then because of GPIO reinitialization - the sync with PHY may
	 * be lost, and the very first frame sent to PHY will be lost as
	 * well. Autonegotiation procedure fixes this, so at very first
	 * time after start we force it.
	 */
	if (link_up && link_inited)
		goto link_set;

	/*
	 * Enable auto-negotiation
	 */
	printf("Auto-negotiation...");
	rv = stm_phy_read(mac, PHY_BMCR, &val);
	if (rv != 0)
		goto out;
	rv = stm_phy_write(mac, PHY_BMCR,
			   val | PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
	if (rv != 0)
		goto out;

	/*
	 * Wait until auto-negotioation complete
	 */
	for (i = 0, val = 0; i < STM32F2_PHY_AUTONEG_TIMEOUT; i++) {
		if (stm_phy_read(mac, PHY_BMSR, &val) != 0)
			continue;
		if (val & PHY_BMSR_AUTN_COMP) {
			printf("completed.\n");
			break;
		}
	}
	if (!(val & PHY_BMSR_AUTN_COMP))
		printf("timeout.\n");

	/*
	 * Get link status
	 */
	rv = stm_phy_link_get(mac, &link_up, &full_dup, &speed);
	if (rv != 0)
		goto out;
	if (!link_up) {
		printf("Link is DOWN.\n");
		rv = -ENETUNREACH;
		goto out;
	}

link_set:
560
	cr_val = STM32F2_MAC->maccr;
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
	printf("%s: link UP ", mac->netdev.name);
	if (speed == 100) {
		printf("(100/");
		cr_val |= STM32F2_MAC_CR_FES;
	} else {
		printf("(10/");
		cr_val &= ~STM32F2_MAC_CR_FES;
	}

	if (full_dup) {
		printf("Full)\n");
		cr_val |= STM32F2_MAC_CR_DM;
	} else {
		printf("Half)\n");
		cr_val &= ~STM32F2_MAC_CR_DM;
	}
577
	STM32F2_MAC->maccr = cr_val;
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594

	link_inited = 1;
	rv = 0;
out:
	return rv;
}

/*
 * Write PHY
 */
static int stm_phy_write(struct stm_eth_dev *mac, u16 reg, u16 val)
{
	u16	adr = mac->phy_adr;
	u32	tmp;
	int	rv;

	tmp = 0;
595
	while ((STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) &&
596
	       (tmp++ < STM32F2_PHY_WRITE_TIMEOUT));
597
	if (STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) {
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
		/*
		 * MII is busy
		 */
		rv = -EBUSY;
		goto out;
	}

	/*
	 * Prepare MII register address value:
	 * - keep CR;
	 * - set PHY device address
	 * - set PHY register address
	 * - set write mode
	 * - set MII Busy
	 */
613
	tmp = STM32F2_MAC->macmiiar;
614
615
616
617
618
619
620
621
622
623
624
625
626
	tmp &= STM32F2_MAC_MIIAR_CR_MSK << STM32F2_MAC_MIIAR_CR_BIT;

	adr &= STM32F2_MAC_MIIAR_PA_MSK;
	tmp |= adr << STM32F2_MAC_MIIAR_PA_BIT;

	reg &= STM32F2_MAC_MIIAR_MR_MSK;
	tmp |= reg << STM32F2_MAC_MIIAR_MR_BIT;

	tmp |= STM32F2_MAC_MIIAR_MW | STM32F2_MAC_MIIAR_MB;

	/*
	 * Write to regs, and wait for completion
	 */
627
628
	STM32F2_MAC->macmiidr = val;
	STM32F2_MAC->macmiiar = tmp;
629
630

	tmp = 0;
631
	while ((STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) &&
632
	       (tmp++ < STM32F2_PHY_WRITE_TIMEOUT));
633
	if (STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) {
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
		/*
		 * Transaction failed: Write timeout
		 */
		rv = -ETIMEDOUT;
		goto out;
	}

	/*
	 * Transaction OK
	 */
	rv = 0;
out:
	return rv;
}

/*
 * Read PHY
 */
static int stm_phy_read(struct stm_eth_dev *mac, u16 reg, u16 *val)
{
	u16	adr = mac->phy_adr;
	u32	tmp;
	int	rv;

	tmp = 0;
659
	while ((STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) &&
660
	       (tmp++ < STM32F2_PHY_READ_TIMEOUT));
661
	if (STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) {
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
		/*
		 * MII is busy
		 */
		rv = -EBUSY;
		goto out;
	}

	/*
	 * Prepare MII register address value:
	 * - keep CR;
	 * - set PHY device address
	 * - set PHY register address
	 * - set read mode
	 * - set MII Busy
	 */
677
	tmp = STM32F2_MAC->macmiiar;
678
679
680
681
682
683
684
685
686
687
688
689
690
	tmp &= STM32F2_MAC_MIIAR_CR_MSK << STM32F2_MAC_MIIAR_CR_BIT;

	adr &= STM32F2_MAC_MIIAR_PA_MSK;
	tmp |= adr << STM32F2_MAC_MIIAR_PA_BIT;

	reg &= STM32F2_MAC_MIIAR_MR_MSK;
	tmp |= reg << STM32F2_MAC_MIIAR_MR_BIT;

	tmp |= STM32F2_MAC_MIIAR_MB;

	/*
	 * Write to reg, and wait for completion
	 */
691
	STM32F2_MAC->macmiiar  = tmp;
692
693

	tmp = 0;
694
	while ((STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) &&
695
	       (tmp++ < STM32F2_PHY_READ_TIMEOUT));
696
	if (STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) {
697
698
699
700
701
702
703
704
705
706
		/*
		 * Transaction failed: read timeout
		 */
		rv = -ETIMEDOUT;
		goto out;
	}

	/*
	 * Transaction OK
	 */
707
	*val = STM32F2_MAC->macmiidr;
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
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731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747

	rv = 0;
out:
	return rv;
}

/*
 * Init STM32F2 MAC buffer descriptors
 */
static void stm_mac_bd_init(struct stm_eth_dev *mac)
{
	int	i;

	/*
	 * Init Tx buffer descriptor
	 */
	mac->tx_bd.stat = STM32F2_DMA_TBD_TCH;
	mac->tx_bd.ctrl = 0;
	mac->tx_bd.buf  = NULL;
	mac->tx_bd.next = &mac->tx_bd;

	/*
	 * Init Rx buffer descriptors
	 */
	for (i = 0; i < PKTBUFSRX; i++) {
		mac->rx_bd[i].stat = STM32F2_DMA_RBD_DMA_OWN;
		mac->rx_bd[i].ctrl = STM32F2_DMA_RBD_RCH |
					 PKTSIZE_ALIGN;
		mac->rx_bd[i].buf  = &mac->rx_buf[i][0];
		mac->rx_bd[i].next = &mac->rx_bd[(i + 1) % PKTBUFSRX];
	}

	/*
	 * Set our internal rx bd pointer to start
	 */
	mac->rx_bd_idx = 0;

	/*
	 * Program DMA with the addresses of descriptor chains
	 */
748
749
	STM32F2_MAC->dmatdlar = (u32)&mac->tx_bd;
	STM32F2_MAC->dmardlar = (u32)&mac->rx_bd[0];
750
751
752
753
754
755
756
757
758
759
760
761
762
763
}

/*
 * Set MAC address
 */
static void stm_mac_address_set(struct stm_eth_dev *mac)
{
	struct eth_device	*netdev = &mac->netdev;

	debug("%s: mac is %#x:%#x:%#x:%#x:%#x:%#x.\n", __func__,
	      netdev->enetaddr[0], netdev->enetaddr[1],
	      netdev->enetaddr[2], netdev->enetaddr[3],
	      netdev->enetaddr[4], netdev->enetaddr[5]);

764
765
766
767
768
769
	STM32F2_MAC->maca0hr = (netdev->enetaddr[5] <<  8) |
			       (netdev->enetaddr[4] <<  0);
	STM32F2_MAC->maca0lr = (netdev->enetaddr[3] << 24) |
			       (netdev->enetaddr[2] << 16) |
			       (netdev->enetaddr[1] <<  8) |
			       (netdev->enetaddr[0] <<  0);
770
771
772
773
774
}

/*
 * Init GPIOs used by MAC
 */
775
static int stm_mac_gpio_init(struct stm_eth_dev *mac)
776
{
777
778
	static struct stm32f2_gpio_dsc	mco_gpio = {0, 8};
	static int			gpio_inited;
779

780
781
	u32	val;
	int	i, rv;
782
783
784
785
786
787
788
789
790

	/*
	 * Init GPIOs only once at start. Otherwise, reiniting then on
	 * each halt/init call from u-boot Net subsystem we may loose
	 * the very first frame sending to net: MAC in this case reports
	 * that frame had been successfully sent, but there is no frame
	 * on wires. Probably, some synchronization with PHY is lost if
	 * we do this GPIO re-initialization.
	 */
791
792
	if (gpio_inited) {
		rv = 0;
793
		goto out;
794
	}
795
796

	/*
797
	 * Enable SYSCFG clock
798
	 */
799
	STM32F2_RCC->apb2enr |= STM32F2_RXX_ENR_SYSCFG;
800
801
802
803

	/*
	 * Configure MC0: PA8
	 */
804
805
806
	rv = stm32f2_gpio_config(&mco_gpio, STM32F2_GPIO_ROLE_MCO);
	if (rv != 0)
		goto out;
807
808
809
810

	/*
	 * Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY
	 */
811
	val  = STM32F2_RCC->cfgr;
812
813
814
815
816
817
818

	val &= ~(STM32F2_RCC_CFGR_MCO1_MSK << STM32F2_RCC_CFGR_MCO1_BIT);
	val |= STM32F2_RCC_CFGR_MCO1_HSE << STM32F2_RCC_CFGR_MCO1_BIT;

	val &= ~(STM32F2_RCC_CFGR_MCO1PRE_MSK << STM32F2_RCC_CFGR_MCO1PRE_BIT);
	val |= STM32F2_RCC_CFGR_MCO1PRE_DIVNO << STM32F2_RCC_CFGR_MCO1PRE_BIT;

819
	STM32F2_RCC->cfgr = val;
820
821
822
823

	/*
	 * Set MII mode
	 */
824
	val = STM32F2_SYSCFG->pmc;
825
826
	val &= STM32F2_SYSCFG_PMC_SEL_MSK << STM32F2_SYSCFG_PMC_SEL_BIT;
	val |= STM32F2_SYSCFG_PMC_SEL_MII << STM32F2_SYSCFG_PMC_SEL_BIT;
827
	STM32F2_SYSCFG->pmc = val;
828
829
830
831
832

	/*
	 * Set GPIOs Alternative function
	 */
	for (i = 0; i < sizeof(mac_gpio)/sizeof(mac_gpio[0]); i++) {
833
834
835
836
		rv = stm32f2_gpio_config(&mac_gpio[i],
					 STM32F2_GPIO_ROLE_ETHERNET);
		if (rv != 0)
			goto out;
837
838
839
	}

	gpio_inited = 1;
840
	rv = 0;
841
out:
842
	return rv;
843
844
845
846
847
848
849
850
851
852
853
854
855
}

/*
 * Init STM32F2 MAC hardware
 */
static int stm_mac_hw_init(struct stm_eth_dev *mac)
{
	u32	tmp, hclk;
	int	i, rv;

	/*
	 * Init GPIOs
	 */
856
857
858
	rv = stm_mac_gpio_init(mac);
	if (rv != 0)
		goto out;
859
860
861
862

	/*
	 * Enable Ethernet clocks
	 */
863
864
865
	STM32F2_RCC->ahb1enr |= STM32F2_RCC_ENR_ETHMACEN   |
				STM32F2_RCC_ENR_ETHMACTXEN |
				STM32F2_RCC_ENR_ETHMACRXEN;
866
867
868
869

	/*
	 * Reset all MAC subsystem internal regs and logic
	 */
870
871
	STM32F2_RCC->ahb1rstr |= STM32F2_RCC_AHB1RSTR_MAC;
	STM32F2_RCC->ahb1rstr &= ~STM32F2_RCC_AHB1RSTR_MAC;
872

873
	STM32F2_MAC->dmabmr |= STM32F2_MAC_DMABMR_SR;
874
	i = 0;
875
	while (STM32F2_MAC->dmabmr & STM32F2_MAC_DMABMR_SR) {
876
877
878
		if (i++ > STM32F2_MAC_INIT_TIMEOUT)
			break;
	}
879
	if (STM32F2_MAC->dmabmr & STM32F2_MAC_DMABMR_SR) {
880
881
882
883
884
885
886
887
888
889
890
891
		printf("%s: failed reset MAC subsystem.\n", __func__);
		rv = -EBUSY;
		goto out;
	}

	/*
	 * Configure DMA:
	 * - address aligned beats (32-bit aligned src & dst addresses),
	 * - fixed burst, and 32 beat max burst lengths,
	 * - round-robin DMA arbitration Rx:Tx<->2:1;
	 * - enable use of separate PBL for Rx and Tx.
	 */
892
893
894
895
896
897
898
	STM32F2_MAC->dmabmr = (32 << STM32F2_MAC_DMABMR_PBL_BIT) |
			      (STM32F2_MAC_DMABMR_RTPR_2_1 <<
			       STM32F2_MAC_DMABMR_RTPR_BIT) |
			      STM32F2_MAC_DMABMR_FB |
			      (32 << STM32F2_MAC_DMABMR_RDP_BIT) |
			      STM32F2_MAC_DMABMR_USP |
			      STM32F2_MAC_DMABMR_AAB;
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917

	/*
	 * Configure Ethernet CSR Clock Range
	 */
	hclk = clock_get(CLOCK_HCLK);
	if (hclk >= 20000000 && hclk < 35000000) {
		/* CSR Clock range between 20-35 MHz */
		tmp = STM32F2_MAC_MIIAR_CR_DIV16 << STM32F2_MAC_MIIAR_CR_BIT;
	} else if (hclk >= 35000000 && hclk < 60000000) {
		/* CSR Clock range between 35-60 MHz */
		tmp = STM32F2_MAC_MIIAR_CR_DIV26 << STM32F2_MAC_MIIAR_CR_BIT;
	} else if (hclk >= 60000000 && hclk < 100000000) {
		/* CSR Clock range between 60-100 MHz */
		tmp = STM32F2_MAC_MIIAR_CR_DIV42 << STM32F2_MAC_MIIAR_CR_BIT;
	} else {
		/* CSR Clock range between 100-120 MHz */
		tmp = STM32F2_MAC_MIIAR_CR_DIV62 << STM32F2_MAC_MIIAR_CR_BIT;
	}

918
	if (STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) {
919
		i = 0;
920
		while ((STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) &&
921
		       (i++ < STM32F2_PHY_READ_TIMEOUT));
922
		if (STM32F2_MAC->macmiiar & STM32F2_MAC_MIIAR_MB) {
923
924
925
926
927
928
929
			/*
			 * MII is busy
			 */
			rv = -EBUSY;
			goto out;
		}
	}
930
	STM32F2_MAC->macmiiar = tmp;
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976

	/*
	 * Init PHY
	 */
	rv = stm_phy_init(mac);
	if (rv != 0)
		goto out;

	/*
	 * Setup link, and complete MAC initialization
	 */
	rv = stm_phy_link_setup(mac);
	if (rv != 0)
		goto out;
out:
	return rv;
}

/*
 * Init STM32F2 MAC and DMA
 */
static int stm_eth_init(struct eth_device *dev, bd_t *bd)
{
	struct stm_eth_dev	*mac = to_stm_eth(dev);
	int			rv;

	/*
	 * Init hw
	 */
	rv = stm_mac_hw_init(mac);
	if (rv != 0)
		goto out;

	/*
	 * Set MAC address
	 */
	stm_mac_address_set(mac);

	/*
	 * Init buffer descriptors
	 */
	stm_mac_bd_init(mac);

	/*
	 * Enable TX
	 */
977
	STM32F2_MAC->maccr |= STM32F2_MAC_CR_TE;
978
979
980
981

	/*
	 * Flush Transmit FIFO
	 */
982
983
	STM32F2_MAC->dmaomr |= STM32F2_MAC_DMAOMR_FTF;
	while (STM32F2_MAC->dmaomr & STM32F2_MAC_DMAOMR_FTF);
984
985
986
987

	/*
	 * Enable RX
	 */
988
	STM32F2_MAC->maccr |= STM32F2_MAC_CR_RE;
989
990
991
992

	/*
	 * Start DMA TX and RX
	 */
993
994
	STM32F2_MAC->dmaomr |= STM32F2_MAC_DMAOMR_ST;
	STM32F2_MAC->dmaomr |= STM32F2_MAC_DMAOMR_SR;
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
out:
	if (rv != 0)
		printf("%s: failed (%d).\n", __func__, rv);
	return rv;
}

/*
 * Send frame
 */
static int stm_eth_send(struct eth_device *dev, volatile void *pkt, int len)
{
	struct stm_eth_dev	*mac = to_stm_eth(dev);
	int			rv, tout;

	if (len > PKTSIZE_ALIGN) {
		printf("%s: frame too long (%d).\n", __func__, len);
		rv = -EINVAL;
		goto out;
	}

	/*
	 * Make sure nothing is txing now
	 */
	if (mac->tx_bd.stat & STM32F2_DMA_TBD_DMA_OWN) {
		printf("%s: busy.\n", __func__);
		rv = -EBUSY;
		goto out;
	}

	/*
	 * Set up BD
	 */
	mac->tx_bd.buf   = pkt;
	mac->tx_bd.ctrl  = len;
	mac->tx_bd.stat |= STM32F2_DMA_TBD_FS | STM32F2_DMA_TBD_LS |
1030
			   STM32F2_DMA_TBD_DMA_OWN;
1031
1032
1033
1034

	/*
	 * If Tx buffer unavailable flag is set, then clear it and resume
	 */
1035
1036
1037
	if (STM32F2_MAC->dmasr & STM32F2_MAC_DMASR_TBUS) {
		STM32F2_MAC->dmasr &= ~STM32F2_MAC_DMASR_TBUS;
		STM32F2_MAC->dmatpdr = 0;
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
	}

	/*
	 * Wait until transmit completes
	 */
	for (tout = 0; tout < STM32F2_MAC_TX_TIMEOUT; tout++) {
		if (mac->tx_bd.stat & STM32F2_DMA_TBD_DMA_OWN)
			continue;
		break;
	}
	if (mac->tx_bd.stat & STM32F2_DMA_TBD_DMA_OWN) {
		printf("%s: timeout.\n", __func__);
		rv = -ETIMEDOUT;
		goto out;
	}

	/*
	 * Tx done.
	 */
	rv = 0;
out:
	return rv;
}

/*
 * Process received frames (if any)
 */
static int stm_eth_recv(struct eth_device *dev)
{
	volatile struct stm_eth_dma_bd	*bd;
	struct stm_eth_dev		*mac = to_stm_eth(dev);
	u32				len;

	/*
	 * Walk through the list of rx bds and process rxed frames until
	 * detect BD owned by DMA
	 */
	while (!(mac->rx_bd[mac->rx_bd_idx].stat & STM32F2_DMA_RBD_DMA_OWN)) {
		bd = &mac->rx_bd[mac->rx_bd_idx];

		/*
		 * RX buf size we use should be enough for storing the whole
		 * ethernet frame with checksum (1518), so the following
		 * shouldn't happen
		 */
		if ((bd->stat & (STM32F2_DMA_RBD_FS | STM32F2_DMA_RBD_LS)) !=
		    (STM32F2_DMA_RBD_FS | STM32F2_DMA_RBD_LS)) {
			printf("%s: warn, frame split (0x%08x).\n", __func__,
				bd->stat);
		}

		/*
		 * Get length, and take 4 CRC bytes into account
		 */
		len  = (bd->stat >> STM32F2_DMA_RBD_FL_BIT) &
		       STM32F2_DMA_RBD_FL_MSK;
		len -= 4;

		/*
		 * Pass frame upper
		 */
		NetReceive(bd->buf, len);

		/*
		 * Mark BD as ready for rx again, and switch to the next BD
		 */
		bd->stat = STM32F2_DMA_RBD_DMA_OWN;
		mac->rx_bd_idx = (mac->rx_bd_idx + 1) % PKTBUFSRX;

		/*
		 * If rx buf unavailable flag is set, clear it and resume
		 * reception
		 */
1111
		if (STM32F2_MAC->dmasr & STM32F2_MAC_DMASR_RBUS) {
1112
1113
1114
1115
			/*
			 * This is actually overflow, frame(s) lost
			 */
			printf("%s: RX overflow.\n", __func__);
1116
1117
			STM32F2_MAC->dmasr &= ~STM32F2_MAC_DMASR_RBUS;
			STM32F2_MAC->dmarpdr = 0;
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1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
		}
	}

	return 0;
}

/*
 * Halt MAC
 */
static void stm_eth_halt(struct eth_device *dev)
{
	/*
	 * Stop DMA, and disable receiver and transmitter
	 */
1132
1133
	STM32F2_MAC->dmaomr &= ~(STM32F2_MAC_DMAOMR_ST | STM32F2_MAC_DMAOMR_SR);
	STM32F2_MAC->maccr  &= ~(STM32F2_MAC_CR_TE | STM32F2_MAC_CR_RE);
1134
}