There are 3 ports (port 0, port 1, port 2) between the AHB bus and the
DDR controller. All of these ports are switched to the synchronous mode
in this patch.

Any of these 3 ports can work in the synchronous mode only when the
system clock is sourced from PLL1. Since the DDR clock is also sourced
from the PLL1 and the CPU clock rate is limited to 120 MHz, we have to
lower the DDR clock to the same 120 MHz.

The source code is configurable so that you can easily switch back to
the DDR asynchronous mode:
 * Synchronous mode configuration (see include/configs/twr-k70f120m.h):
    * KINETIS_PLL1_VDIV = 24 (we have to limit DDR clock to 120 MHz)
    * KINETIS_MCGOUT_PLL1 is set (system clock is sourced from PLL1)
    * CONFIG_KINETIS_DDR_SYNC is set
 * Asynchronous mode configuration (see include/configs/twr-k70f120m.h):
    * KINETIS_PLL1_VDIV = 30 (we want the maximum DDR clock: 150 MHz)
    * KINETIS_MCGOUT_PLL1 is not set (system clock is sourced from PLL0)
    * CONFIG_KINETIS_DDR_SYNC is not set

The DDR synchronous mode improves performance: 37.27 BogoMIPS in
synchronous mode (DDR @ 120 MHz) against 11.03 BogoMIPS in asynchronous
mode (DDR @ 150 MHz) in Linux.