Commit 0e7179d5 authored by Sergei Poselenov's avatar Sergei Poselenov

RT #73025. LPC178x: NOR Flash support. Environment in flash.

parent 75e64206
......@@ -117,8 +117,13 @@
/* EMC data pins (DQ0..DQ31) */
#define LPC178X_EMC_DATA_PINS 31
#if !defined(CONFIG_SYS_FLASH_CS)
/* EMC row/column address pins (A0..A11) */
#define LPC178X_EMC_ADDR_PINS 12
#else
/* ..and NOR Flash pins up to A22 */
#define LPC178X_EMC_ADDR_PINS 22
#endif
/*
* Dynamic Memory Control register
......@@ -197,6 +202,20 @@ struct lpc178x_emc_dy_regs {
u32 rsv0[6];
};
/*
* EMC controls for Static Memory CS. Each block occupies 0x20 bytes.
*/
struct lpc178x_emc_st_regs {
u32 cfg; /* Static Memory Configuration register */
u32 we; /* CS to WE delay register */
u32 oe; /* CS to OE delay register */
u32 rd; /* CS to Read delay register */
u32 page; /* async page mode access delay */
u32 wr; /* CS to Write delay register */
u32 ta; /* number of turnaround cycles */
u32 rsv0[1];
};
/*
* EMC (External Memory Controller) register map
* Should be mapped at 0x2009C000.
......@@ -237,6 +256,9 @@ struct lpc178x_emc_regs {
/* 0x2009C100 */
struct lpc178x_emc_dy_regs dy[4]; /* 4 DRAM chips are possible */
u32 rsv3[32];
/* 0x2009C200 */
struct lpc178x_emc_st_regs st[4]; /* 4 Static RAM devices (flash) */
};
#define LPC178X_EMC_BASE (LPC178X_AHB_PERIPH_BASE + 0x0001C000)
......@@ -328,6 +350,22 @@ static const struct lpc178x_gpio_pin_config ea_lpc1788_gpio[] = {
/* P1.17 (D) = RMII MDIO */
{{1, 17}, LPC178X_GPIO_CONFIG_D(1, LPC178X_NO_PULLUP, 0, 0, 0, 0)},
#endif /* CONFIG_LPC178X_ETH */
#ifdef CONFIG_SYS_FLASH_CS
/*
* GPIO configuration for Flash.
*/
/* P4.30 (D) = NOR FLash CS0 */
{{4, 30}, LPC178X_GPIO_CONFIG_D(1, LPC178X_NO_PULLUP, 0, 0, 1, 0)},
/* P4.24 (D) = NOR FLash BOE */
{{4, 24}, LPC178X_GPIO_CONFIG_D(1, LPC178X_NO_PULLUP, 0, 0, 1, 0)},
/* P4.25 (D) = NOR FLash BWE */
{{4, 25}, LPC178X_GPIO_CONFIG_D(1, LPC178X_NO_PULLUP, 0, 0, 1, 0)},
/* P4.26 (D) = Data Buffer BLS0 */
{{4, 26}, LPC178X_GPIO_CONFIG_D(1, LPC178X_NO_PULLUP, 0, 0, 1, 0)},
/* P4.27 (D) = Data Buffer BLS1 */
{{4, 27}, LPC178X_GPIO_CONFIG_D(1, LPC178X_NO_PULLUP, 0, 0, 1, 0)},
#endif
};
/*
......@@ -357,7 +395,10 @@ static void gpio_init(void)
for (dsc.pin = 0; dsc.pin <= LPC178X_EMC_DATA_PINS; dsc.pin++)
lpc178x_gpio_config(&dsc, LPC178X_GPIO_EMC_REGVAL);
/* Configure EMC row/column address pins (A0..A11) */
/*
* Configure EMC row/column address pins (A0..A11) and
* NOR FLash address pins.
*/
dsc.port = 4;
for (dsc.pin = 0; dsc.pin <= LPC178X_EMC_ADDR_PINS; dsc.pin++)
lpc178x_gpio_config(&dsc, LPC178X_GPIO_EMC_REGVAL);
......@@ -369,8 +410,45 @@ static void gpio_init(void)
*/
int board_init(void)
{
volatile struct lpc178x_emc_st_regs *st;
/*
* Enable power on EMC
*/
lpc178x_periph_enable(LPC178X_SCC_PCONP_PCEMC_MSK, 1);
/*
* Clock delay for EMC
*/
LPC178X_SCC->emcdlyctl =
(LPC178X_EMC_CMDDLY << LPC178X_SCC_EMCDLYCTL_CMDDLY_BITS) |
(LPC178X_EMC_FBCLKDLY << LPC178X_SCC_EMCDLYCTL_FBCLKDLY_BITS);
/*
* Enable EMC
*/
LPC178X_EMC->emcctrl = LPC178X_EMC_CTRL_EN_MSK;
/*
* Little-endian mode
*/
LPC178X_EMC->emccfg = 0;
/*
* Enable GPIO pins
*/
gpio_init();
#ifdef CONFIG_SYS_FLASH_CS
/* Set timing for flash */
st = &LPC178X_EMC->st[CONFIG_SYS_FLASH_CS];
st->cfg = CONFIG_SYS_FLASH_CFG;
st->we = CONFIG_SYS_FLASH_WE;
st->oe = CONFIG_SYS_FLASH_OE;
st->rd = CONFIG_SYS_FLASH_RD;
st->page = CONFIG_SYS_FLASH_PAGE;
st->wr = CONFIG_SYS_FLASH_WR;
st->ta = CONFIG_SYS_FLASH_TA;
#endif
return 0;
}
......@@ -406,27 +484,6 @@ int dram_init(void)
dy = &LPC178X_EMC->dy[CONFIG_SYS_RAM_CS];
/*
* Enable power on EMC
*/
lpc178x_periph_enable(LPC178X_SCC_PCONP_PCEMC_MSK, 1);
/*
* Clock delay
*/
LPC178X_SCC->emcdlyctl =
(LPC178X_EMC_CMDDLY << LPC178X_SCC_EMCDLYCTL_CMDDLY_BITS) |
(LPC178X_EMC_FBCLKDLY << LPC178X_SCC_EMCDLYCTL_FBCLKDLY_BITS);
/*
* Enable EMC
*/
LPC178X_EMC->emcctrl = LPC178X_EMC_CTRL_EN_MSK;
/*
* Little-endian mode
*/
LPC178X_EMC->emccfg = 0;
/*
* Address mapping (see Table 133 from the LPC178x/7x User Manual)
*/
......@@ -515,3 +572,15 @@ int board_eth_init(bd_t *bis)
}
#endif
#ifdef CONFIG_FLASH_CFI_LEGACY
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI flash */
info->portwidth = FLASH_CFI_16BIT;
info->chipwidth = FLASH_CFI_BY16;
info->interface = FLASH_CFI_X16;
return 1;
} else
return 0;
}
#endif
......@@ -55,7 +55,6 @@ void cortex_m3_soc_init(void)
*/
lpc178x_periph_enable(uart_pconp_mask[CONFIG_LPC178X_UART_PORT], 1);
#endif
/*
* Configure the memory protection unit (MPU) to allow full access to
* the whole 4GB address space.
......
......@@ -61,6 +61,7 @@
#define SST39LF800 0x2781
#define SST39LF160 0x2782
#define SST39VF1601 0x234b
#define SST39VF3201 0x235b
#define SST39LF512 0x00D4
#define SST39LF010 0x00D5
#define SST39LF020 0x00D6
......@@ -329,6 +330,26 @@ static const struct amd_flash_info jedec_table[] = {
}
},
#endif
#ifdef CONFIG_SYS_FLASH_LEGACY_2Mx16
/* Taken from the Linux jedec_probe.c */
{
.mfr_id = (u16)SST_MANUFACT,
.dev_id = SST39VF3201,
.name = "SST SST39VF3201",
.uaddr = {
[1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
},
.DevSize = SIZE_4MiB,
.CmdSet = CFI_CMDSET_AMD_LEGACY,
.NumEraseRegions= 4,
.regions = {
ERASEINFO(0x01000, 256),
ERASEINFO(0x01000, 256),
ERASEINFO(0x01000, 256),
ERASEINFO(0x01000, 256),
}
},
#endif
};
static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base)
......
......@@ -29,7 +29,7 @@
/*
* Disable debug messages
*/
#undef DEBUG
//#undef DEBUG
/*
* This is an ARM Cortex-M3 CPU core
......@@ -183,12 +183,41 @@
/*
* Configuration of the external Flash memory
*/
#define CONFIG_SYS_NO_FLASH
/* Define this to enable NOR FLash support */
#define CONFIG_SYS_FLASH_CS 0
#if defined(CONFIG_SYS_FLASH_CS)
#define CONFIG_SYS_FLASH_CFG 0x81 /* 16 bit, Byte Lane enabled */
#define CONFIG_SYS_FLASH_WE 0x2
#define CONFIG_SYS_FLASH_OE 0x2
#define CONFIG_SYS_FLASH_RD 0x1f
#define CONFIG_SYS_FLASH_PAGE 0x1f
#define CONFIG_SYS_FLASH_WR 0x1f
#define CONFIG_SYS_FLASH_TA 0x1f
#define CONFIG_SYS_FLASH_BANK1_BASE 0x80000000 /* hardwired for CS0 */
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_FLASH_CFI_LEGACY 1
#define CONFIG_SYS_FLASH_LEGACY_2Mx16 1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BANK1_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 1024
/*
* Store env in memory only
* Store env in flash.
*/
#define CONFIG_ENV_IS_IN_FLASH
#else
/*
* Store env in memory only, if no flash.
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#endif
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BANK1_BASE
#define CONFIG_INFERNO 1
......
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