Commit 12b7c142 authored by Vladimir Khusainov's avatar Vladimir Khusainov

RT76491 Enabled the caches.

parent fe65e8bf
......@@ -24,20 +24,86 @@
#include "soc.h"
/*
* Memory Protection Unit (MPU) register map
* Memory Protection Unit (MPU) registers map
*
* See Chapter 18 of the K60 Reference Manual (page 409)
*/
struct kinetis_mpu_regs {
u32 cesr; /* Control/Error Status Register */
u32 cesr;
};
/*
* MPU registers base
*/
#define KINETIS_MPU_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0000D000)
#define KINETIS_MPU ((volatile struct kinetis_mpu_regs *) \
KINETIS_MPU_BASE)
#define KINETIS_MPU_BASE (KINETIS_AIPS0PERIPH_BASE + 0x0000D000)
#define KINETIS_MPU ((volatile struct kinetis_mpu_regs *) \
KINETIS_MPU_BASE)
/*
* Cache interface registers map
*
* See Chapter 24 of the K70 Reference Manual
*/
struct kinetis_cache_regs {
u32 ccr;
u32 clcr;
u32 csar;
u32 ccvr;
u32 unused[4];
u32 crmr;
};
/*
* Cache interface registers base
*/
#define KINETIS_PC_CACHE_BASE 0xE0082000
#define KINETIS_PC_CACHE ((volatile struct kinetis_cache_regs *) \
KINETIS_PC_CACHE_BASE)
#define KINETIS_PS_CACHE_BASE 0xE0082800
#define KINETIS_PS_CACHE ((volatile struct kinetis_cache_regs *) \
KINETIS_PS_CACHE_BASE)
/*
* Enable the caches if so configured
*/
static void kinetis_cache_init(void)
{
#if defined(CONFIG_KINETIS_PC_CACHE_ON)
/*
* This sets up the following cache modes for the I/D bus cache:
* - on-chip Flash => write-through
* - DRAM controller (0x08000000) => write-through
* - FlexNVM => non-cacheable
* - FlexBus (Alias) => non-cacheable
*/
KINETIS_PC_CACHE->crmr = 0xA0000000;
/*
* This invalidates the I/D bus cache and
* and then enables the cache and write buffer
*/
KINETIS_PC_CACHE->ccr = 0x85000003;
while (KINETIS_PC_CACHE->ccr & 0x80000000);
#endif
#if defined(CONFIG_KINETIS_PS_CACHE_ON)
/*
* This sets up the following cache modes for the System bus cache:
* - FlexBus (external memory - write-back) => non-cacheable
* - DRAM controller (0x70000000) => write-back
* - DRAM controller (0x80000000) => non-cacheable
* - FlexBus (external memory - write-through) => non-cacheable
*/
KINETIS_PS_CACHE->crmr = 0x00030000;
/*
* This invalidates the System bus cache and
* and then enables the cache and write buffer
*/
KINETIS_PS_CACHE->ccr = 0x85000003;
while (KINETIS_PS_CACHE->ccr & 0x80000000);
#endif
}
/*
* SoC configuration code that cannot be put into drivers
......@@ -63,5 +129,10 @@ void cortex_m3_soc_init(void)
* Disable the MPU to let the Ethernet module access the SRAM
*/
KINETIS_MPU->cesr = 0;
/*
* Enable the caches if so configured
*/
kinetis_cache_init();
}
#endif
......@@ -137,6 +137,14 @@
*/
#undef CONFIG_USE_IRQ
/*
* Cache configuration
*/
#define CONFIG_KINETIS_PC_CACHE_ON
/* #undef CONFIG_KINETIS_PC_CACHE_ON */
#define CONFIG_KINETIS_PS_CACHE_ON
/* #undef CONFIG_KINETIS_PS_CACHE_ON */
/*
* Configuration of the external DDR2 SDRAM memory
*/
......@@ -144,7 +152,8 @@
#define CONFIG_KINETIS_DDR_SYNC /* DDR synchronous mode */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_CS 0
#define CONFIG_SYS_RAM_BASE 0x80000000
#define CONFIG_SYS_RAM_BASE 0x70000000
#define CONFIG_SYS_RAM_ALIAS 0x80000000
#define CONFIG_SYS_RAM_SIZE (128 * 1024 * 1024)
/*
......@@ -167,7 +176,7 @@
*/
#define CONFIG_SYS_MALLOC_EXT_LEN (1024 * 1024)
#define CONFIG_SYS_MALLOC_EXT_BASE \
(CONFIG_SYS_RAM_BASE + CONFIG_SYS_RAM_SIZE - CONFIG_SYS_MALLOC_EXT_LEN)
(CONFIG_SYS_RAM_ALIAS + CONFIG_SYS_RAM_SIZE - CONFIG_SYS_MALLOC_EXT_LEN)
/*
* The generic code still needs CONFIG_SYS_MALLOC_LEN to calculate the base
* address of the global data (`gd`) structure.
......@@ -340,7 +349,7 @@
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80000000\0" \
"loadaddr=0x08000000\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:eth0:off\0" \
......
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