Commit 15db5150 authored by Yuri Tikhonov's avatar Yuri Tikhonov
Browse files

RT106081. STM32F4 FB: support on STM32F7-SOM

To enable splash:
  tftp clock24.bmp
  prot off 60fa0000 +${filesize}
  era 60fa0000 +${filesize}
  cp.b ${loadaddr} 60fa0000 ${filesize}
  setenv splashimage 60fa0000

BMP in this example is available here:
  http://localhost:8000/Projects/RT89558?action=AttachFile&do=get&target=clock24.bmp

Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
parent 75e3a51f
......@@ -193,70 +193,6 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
#ifdef CONFIG_VIDEO_STM32F4_LTDC
static const struct stm32f2_gpio_dsc ltdc_iomux[] = {
#if defined(CONFIG_SYS_STM32F7)
/*
* STM32F7-SOM
*/
/* PI14 = LCD_CLK */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_14},
/* PK7 = LCD_DE */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_7},
/* PI12 = LCD_HSYNC */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_12},
/* PI13 = LCD_VSYNC */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_13},
/* PJ12 = LCD_B0 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_12},
/* PJ13 = LCD_B1 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_13},
/* PJ14 = LCD_B2 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_14},
/* PJ15 = LCD_B3 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_15},
/* PK3 = LCD_B4 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_3},
/* PK4 = LCD_B5 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_4},
/* PK5 = LCD_B6 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_5},
/* PK6 = LCD_B7 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_6},
/* PJ7 = LCD_G0 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_7},
/* PJ8 = LCD_G1 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_8},
/* PJ9 = LCD_G2 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_9},
/* PJ10 = LCD_G3 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_10},
/* PJ11 = LCD_G4 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_11},
/* PK0 = LCD_G5 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_0},
/* PK1 = LCD_G6 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_1},
/* PK2 = LCD_G7 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_2},
/* PI15 = LCD_R0 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_15},
/* PJ0 = CD_R1 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_0},
/* PJ1 = LCD_R2 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_1},
/* PJ2 = LCD_R3 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_2},
/* PJ3 = LCD_R4 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_3},
/* PJ4 = LCD_R5 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_4},
/* PJ5 = LCD_R6 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_5},
/* PJ6 = LCD_R7 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_6},
#else
/*
* STM-SOM
*/
/* PG7 = LCD_CLK */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_7},
/* PF10 = LCD_DE */
......@@ -305,7 +241,6 @@ static const struct stm32f2_gpio_dsc ltdc_iomux[] = {
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_12},
/* PG6 = LCD_R7 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_6},
#endif
};
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
......
......@@ -163,6 +163,67 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
#endif
};
#ifdef CONFIG_VIDEO_STM32F4_LTDC
static const struct stm32f2_gpio_dsc ltdc_iomux[] = {
/* PI14 = LCD_CLK */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_14},
/* PK7 = LCD_DE */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_7},
/* PI12 = LCD_HSYNC */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_12},
/* PI13 = LCD_VSYNC */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_13},
/* PJ12 = LCD_B0 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_12},
/* PJ13 = LCD_B1 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_13},
/* PJ14 = LCD_B2 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_14},
/* PJ15 = LCD_B3 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_15},
/* PK3 = LCD_B4 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_3},
/* PK4 = LCD_B5 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_4},
/* PK5 = LCD_B6 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_5},
/* PK6 = LCD_B7 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_6},
/* PJ7 = LCD_G0 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_7},
/* PJ8 = LCD_G1 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_8},
/* PJ9 = LCD_G2 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_9},
/* PJ10 = LCD_G3 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_10},
/* PJ11 = LCD_G4 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_11},
/* PK0 = LCD_G5 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_0},
/* PK1 = LCD_G6 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_1},
/* PK2 = LCD_G7 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_2},
/* PI15 = LCD_R0 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_15},
/* PJ0 = CD_R1 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_0},
/* PJ1 = LCD_R2 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_1},
/* PJ2 = LCD_R3 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_2},
/* PJ3 = LCD_R4 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_3},
/* PJ4 = LCD_R5 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_4},
/* PJ5 = LCD_R6 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_5},
/* PJ6 = LCD_R7 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_6},
};
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
/*
* Init FMC/FSMC GPIOs based
*/
......@@ -186,6 +247,29 @@ out:
return rv;
}
#ifdef CONFIG_VIDEO_STM32F4_LTDC
/*
* Initialize LCD pins
*/
static int ltdc_setup_iomux(void)
{
int rv = 0;
int i;
/*
* Connect GPIOs to FMC controller
*/
for (i = 0; i < ARRAY_SIZE(ltdc_iomux); i++) {
rv = stm32f2_gpio_config(&ltdc_iomux[i],
STM32F2_GPIO_ROLE_LTDC);
if (rv)
break;
}
return rv;
}
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
/*
* Early hardware init.
*/
......@@ -208,6 +292,12 @@ int board_init(void)
#endif
#ifdef CONFIG_VIDEO_STM32F4_LTDC
rv = ltdc_setup_iomux();
if (rv)
return rv;
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
Done:
return 0;
}
......
......@@ -303,6 +303,46 @@
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
/*
* Framebuffer configuration
*/
#define CONFIG_LCD
#ifdef CONFIG_LCD
#define CONFIG_FB_ADDR CONFIG_DMAMEM_BASE
#define CONFIG_VIDEO_STM32F4_LTDC
#define CONFIG_STM32_LTDC_PIXCLK (9 * 1000 * 1000)
#define LCD_EMCRAFT_IOT_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP
#undef CONFIG_CMD_BMP
#define CONFIG_BMP_24BPP
#define LCD_BPP LCD_COLOR24
#ifdef LCD_EMCRAFT_IOT_LCD
# define CONFIG_STM32F4_LTDC_XRES 480
# define CONFIG_STM32F4_LTDC_YRES 272
# define CONFIG_STM32F4_LTDC_BPP LCD_BPP
# define CONFIG_STM32F4_LTDC_LEFT_MARGIN 2
# define CONFIG_STM32F4_LTDC_HSYNC_LEN 41
# define CONFIG_STM32F4_LTDC_RIGHT_MARGIN 2
# define CONFIG_STM32F4_LTDC_UPPER_MARGIN 2
# define CONFIG_STM32F4_LTDC_VSYNC_LEN 10
# define CONFIG_STM32F4_LTDC_LOWER_MARGIN 2
#elif defined(CONFIG_VIDEO_STM32F4_LTDC)
# error "STM32F7 LTDC is enabled but no LCD configured"
#endif
#endif /* CONFIG_LCD */
/*
* Enable all those monitor commands that are needed
*/
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment