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Sami Nurmenniemi
u-boot-stm32
Commits
29f5b1fd
Commit
29f5b1fd
authored
Dec 22, 2013
by
Vladimir Khusainov
Browse files
RT92026 Support for SDRAM added on the STM32F429 Discovery.
Test = mtest is passing.
parent
8c55cb3e
Changes
2
Hide whitespace changes
Inline
Side-by-side
board/stm/stm32f429-discovery/board.c
View file @
29f5b1fd
...
...
@@ -43,111 +43,83 @@
DECLARE_GLOBAL_DATA_PTR
;
static
const
struct
stm32f2_gpio_dsc
ext_ram_fsmc_fmc_gpio
[]
=
{
/* Chip is
UFBGA176
, see DM00077036.pdf for details */
/*
N15
, FMC_D15 */
/* Chip is
LQFP144
, see DM00077036.pdf for details */
/*
79
, FMC_D15 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_10
},
/*
P14
, FMC_D14 */
/*
78
, FMC_D14 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_9
},
/*
P15
, FMC_D13 */
/*
77
, FMC_D13 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_8
},
/*
R11
, FMC_D12 */
/*
68
, FMC_D12 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_15
},
/*
P11
, FMC_D11 */
/*
67
, FMC_D11 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_14
},
/*
N11
, FMC_D10 */
/*
66
, FMC_D10 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_13
},
/*
R10
, FMC_D9 */
/*
65
, FMC_D9 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_12
},
/*
P10
, FMC_D8 */
/*
64
, FMC_D8 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_11
},
/*
R9
, FMC_D7 */
/*
63
, FMC_D7 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_10
},
/*
P9
, FMC_D6 */
/*
60
, FMC_D6 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_9
},
/*
P8
, FMC_D5 */
/*
59
, FMC_D5 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_8
},
/*
R
8, FMC_D4 */
/*
5
8, FMC_D4 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_7
},
/*
C12
, FMC_D3 */
/*
115
, FMC_D3 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_1
},
/*
B12
, FMC_D2 */
/*
114
, FMC_D2 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_0
},
/*
L14
, FMC_D1 */
/*
86
, FMC_D1 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_15
},
/*
M14
, FMC_D0 */
/*
85
, FMC_D0 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_14
},
/* A3, FMC_NBL1 */
/* 142, FMC_NBL1 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_1
},
/*
A4
, FMC_NBL0 */
/*
141
, FMC_NBL0 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_0
},
/* D10, FMC_NOE */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_4
},
/* C11, FMC_NWE */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_5
},
/* B3, FMC_A22 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_6
},
/* B2, FMC_A21 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_5
},
/* B1, FMC_A20 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_4
},
/* A1, FMC_A19 */
{
STM32F2_GPIO_PORT_E
,
STM32F2_GPIO_PIN_3
},
/* M15, FMC_A18 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_13
},
/* N13, FMC_A17 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_12
},
/* N14, FMC_A16 */
{
STM32F2_GPIO_PORT_D
,
STM32F2_GPIO_PIN_11
},
/* K13, FMC_A15, BA1 */
/* 90, FMC_A15, BA1 */
{
STM32F2_GPIO_PORT_G
,
STM32F2_GPIO_PIN_5
},
/*
K14
, FMC_A14, BA0 */
/*
89
, FMC_A14, BA0 */
{
STM32F2_GPIO_PORT_G
,
STM32F2_GPIO_PIN_4
},
/* K15, FMC_A13 */
{
STM32F2_GPIO_PORT_G
,
STM32F2_GPIO_PIN_3
},
/* L15, FMC_A12 */
{
STM32F2_GPIO_PORT_G
,
STM32F2_GPIO_PIN_2
},
/* M7, FMC_A11 */
/* 57, FMC_A11 */
{
STM32F2_GPIO_PORT_G
,
STM32F2_GPIO_PIN_1
},
/*
N7
, FMC_A10 */
/*
56
, FMC_A10 */
{
STM32F2_GPIO_PORT_G
,
STM32F2_GPIO_PIN_0
},
/*
P7
, FMC_A9 */
/*
55
, FMC_A9 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_15
},
/*
R7
, FMC_A8 */
/*
54
, FMC_A8 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_14
},
/*
N6
, FMC_A7 */
/*
53
, FMC_A7 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_13
},
/*
P6
, FMC_A6 */
/*
50
, FMC_A6 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_12
},
/*
K3
, FMC_A5 */
/*
15
, FMC_A5 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_5
},
/*
J3
, FMC_A4 */
/*
14
, FMC_A4 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_4
},
/*
J2
, FMC_A3 */
/*
13
, FMC_A3 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_3
},
/*
H
2, FMC_A2 */
/*
1
2, FMC_A2 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_2
},
/*
H3
, FMC_A1 */
/*
11
, FMC_A1 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_1
},
/*
E2
, FMC_A0 */
/*
10
, FMC_A0 */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_0
},
/* SDRAM only */
/* M4, SDRAM_NE */
{
STM32F2_GPIO_PORT_C
,
STM32F2_GPIO_PIN_2
},
/* R6, SDRAM_NRAS */
/* 136, SDRAM_NE */
{
STM32F2_GPIO_PORT_B
,
STM32F2_GPIO_PIN_6
},
/* 49, SDRAM_NRAS */
{
STM32F2_GPIO_PORT_F
,
STM32F2_GPIO_PIN_11
},
/*
B7
, SDRAM_NCAS */
/*
132
, SDRAM_NCAS */
{
STM32F2_GPIO_PORT_G
,
STM32F2_GPIO_PIN_15
},
/* J4, SDRAM_NWE */
{
STM32F2_GPIO_PORT_H
,
STM32F2_GPIO_PIN_5
},
/* M5, SDRAM_CKE */
{
STM32F2_GPIO_PORT_C
,
STM32F2_GPIO_PIN_3
},
/* H14, SDRAM_CLK */
/* 26, SDRAM_NWE */
{
STM32F2_GPIO_PORT_C
,
STM32F2_GPIO_PIN_0
},
/* 135, SDRAM_CKE */
{
STM32F2_GPIO_PORT_B
,
STM32F2_GPIO_PIN_5
},
/* 93, SDRAM_CLK */
{
STM32F2_GPIO_PORT_G
,
STM32F2_GPIO_PIN_8
},
};
...
...
@@ -214,34 +186,34 @@ static inline u32 _ns2clk(u32 ns, u32 freq)
#define NS2CLK(ns) (_ns2clk(ns, freq))
/*
* Following are timings for
M12L2561616A-6BI
, from corresponding datasheet
* Following are timings for
IS42S16400J
, from corresponding datasheet
*/
#define SDRAM_CAS 3
#define SDRAM_NB 1
/* Number of banks */
#define SDRAM_MWID 1
/* 16 bit memory */
#define SDRAM_NR 0x
2
/* 1
3
-bit row */
#define SDRAM_NC 0x
1
/*
9
-bit col */
#define SDRAM_NR 0x
1
/* 1
2
-bit row */
#define SDRAM_NC 0x
0
/*
8
-bit col */
#define SDRAM_TRRD NS2CLK(1
2
)
#define SDRAM_TRCD NS2CLK(1
8
)
#define SDRAM_TRP NS2CLK(1
8
)
#define SDRAM_TRAS NS2CLK(42)
#define SDRAM_TRC NS2CLK(6
0
)
#define SDRAM_TRFC NS2CLK(6
0
)
#define SDRAM_TRRD
(
NS2CLK(1
4) - 1
)
#define SDRAM_TRCD
(
NS2CLK(1
5) - 1
)
#define SDRAM_TRP
(
NS2CLK(1
5) - 1
)
#define SDRAM_TRAS
(
NS2CLK(42)
- 1)
#define SDRAM_TRC
(
NS2CLK(6
3) - 1
)
#define SDRAM_TRFC
(
NS2CLK(6
3) - 1
)
#define SDRAM_TCDL (1 - 1)
#define SDRAM_TRDL
NS2CLK(12
)
#define SDRAM_TRDL
(2 - 1
)
#define SDRAM_TBDL (1 - 1)
#define SDRAM_TREF
(NS2CLK(64000000 / 8192) - 20)
#define SDRAM_TREF
1386
#define SDRAM_TCCD (1 - 1)
#define SDRAM_TXSR
SDRAM_TRFC
/* Row cycle time after precharge */
#define SDRAM_TXSR
(NS2CLK(70)-1)
/* Row cycle time after precharge */
#define SDRAM_TMRD (3 - 1)
/* Page 10, Mode Register Set */
/* Last data in to row precharge, need also comply ineq on page 1648 */
#define SDRAM_TWR max(\
(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD
- 1
)), \
(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP
- 2
)\
)
int
dram_init
(
void
)
...
...
@@ -260,6 +232,11 @@ int dram_init(void)
freq
=
clock_get
(
CLOCK_HCLK
)
/
CONFIG_SYS_RAM_FREQ_DIV
;
STM32_SDRAM_FMC
->
sdcr1
=
(
CONFIG_SYS_RAM_FREQ_DIV
<<
FMC_SDCR_SDCLK_SHIFT
|
0
<<
FMC_SDCR_RPIPE_SHIFT
|
1
<<
FMC_SDCR_RBURST_SHIFT
);
STM32_SDRAM_FMC
->
sdcr2
=
(
CONFIG_SYS_RAM_FREQ_DIV
<<
FMC_SDCR_SDCLK_SHIFT
|
SDRAM_CAS
<<
FMC_SDCR_CAS_SHIFT
|
SDRAM_NB
<<
FMC_SDCR_NB_SHIFT
|
...
...
@@ -270,7 +247,11 @@ int dram_init(void)
1
<<
FMC_SDCR_RBURST_SHIFT
);
STM32_SDRAM_FMC
->
sdtr1
=
(
STM32_SDRAM_FMC
->
sdtr2
=
(
SDRAM_TRP
<<
FMC_SDTR_TRP_SHIFT
|
SDRAM_TRC
<<
FMC_SDTR_TRC_SHIFT
);
STM32_SDRAM_FMC
->
sdtr2
=
(
SDRAM_TRCD
<<
FMC_SDTR_TRCD_SHIFT
|
SDRAM_TRP
<<
FMC_SDTR_TRP_SHIFT
|
SDRAM_TWR
<<
FMC_SDTR_TWR_SHIFT
|
...
...
@@ -280,18 +261,18 @@ int dram_init(void)
SDRAM_TMRD
<<
FMC_SDTR_TMRD_SHIFT
);
STM32_SDRAM_FMC
->
sdcmr
=
FMC_SDCMR_BANK_
1
|
FMC_SDCMR_MODE_START_CLOCK
;
STM32_SDRAM_FMC
->
sdcmr
=
FMC_SDCMR_BANK_
2
|
FMC_SDCMR_MODE_START_CLOCK
;
udelay
(
200
);
/* 200 us delay, page 10, "Power-Up" */
FMC_BUSY_WAIT
();
STM32_SDRAM_FMC
->
sdcmr
=
FMC_SDCMR_BANK_
1
|
FMC_SDCMR_MODE_PRECHARGE
;
STM32_SDRAM_FMC
->
sdcmr
=
FMC_SDCMR_BANK_
2
|
FMC_SDCMR_MODE_PRECHARGE
;
udelay
(
100
);
FMC_BUSY_WAIT
();
STM32_SDRAM_FMC
->
sdcmr
=
(
FMC_SDCMR_BANK_
1
|
FMC_SDCMR_MODE_AUTOREFRESH
|
FMC_SDCMR_BANK_
2
|
FMC_SDCMR_MODE_AUTOREFRESH
|
7
<<
FMC_SDCMR_NRFS_SHIFT
);
...
...
@@ -304,7 +285,7 @@ int dram_init(void)
#define SDRAM_MODE_BL 0
#define SDRAM_MODE_CAS SDRAM_CAS
STM32_SDRAM_FMC
->
sdcmr
=
FMC_SDCMR_BANK_
1
|
STM32_SDRAM_FMC
->
sdcmr
=
FMC_SDCMR_BANK_
2
|
(
SDRAM_MODE_BL
<<
SDRAM_MODE_BL_SHIFT
|
SDRAM_MODE_CAS
<<
SDRAM_MODE_CAS_SHIFT
...
...
@@ -314,7 +295,7 @@ int dram_init(void)
FMC_BUSY_WAIT
();
STM32_SDRAM_FMC
->
sdcmr
=
FMC_SDCMR_BANK_
1
|
FMC_SDCMR_MODE_NORMAL
;
STM32_SDRAM_FMC
->
sdcmr
=
FMC_SDCMR_BANK_
2
|
FMC_SDCMR_MODE_NORMAL
;
FMC_BUSY_WAIT
();
...
...
include/configs/stm32f429-discovery.h
View file @
29f5b1fd
...
...
@@ -139,8 +139,8 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024)
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
#define CONFIG_SYS_RAM_BASE 0x
C
0000000
#define CONFIG_SYS_RAM_FREQ_DIV
2
#define CONFIG_SYS_RAM_BASE 0x
D
0000000
/*
* No external Flash
...
...
@@ -256,7 +256,7 @@
#define CONFIG_HOSTNAME stm32f4x9-som
#define CONFIG_BOOTARGS "stm32_platform=stm32f4x9-som "\
"console=ttyS0,115200 panic=10"
#define LOADADDR "0x
C
0007FC0"
#define LOADADDR "0x
D
0007FC0"
#define REV_EXTRA_ENV \
"envmboot=run addip;bootm ${envmaddr}\0" \
...
...
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