RT72064. stm32f2: access FLASH, RCC, SYSCFG regs with macros

Don't declare & init local volatile pointer vars to access these
regs in each function, which need these. Use macros instead.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

cpu/arm_cortexm3/stm32f2/clock.c

@@ -215,32 +215,26 @@ static u32 clock_val[CLOCK_END];
  */
 static void clock_setup(void)
 {
-	volatile struct stm32f2_rcc_regs	*rcc_regs;
 	u32	val;
 	int	i;
 
-	/*
-	 * Get RCC regs base
-	 */
-	rcc_regs = (struct stm32f2_rcc_regs *)STM32F2_RCC_BASE;
-
 	/*
 	 * Enable HSE, and wait it becomes ready
 	 */
-	rcc_regs->cr |= STM32F2_RCC_CR_HSEON;
+	STM32F2_RCC->cr |= STM32F2_RCC_CR_HSEON;
 	for (i = 0; i < STM32F2_HSE_STARTUP_TIMEOUT; i++) {
-		if (rcc_regs->cr & STM32F2_RCC_CR_HSERDY)
+		if (STM32F2_RCC->cr & STM32F2_RCC_CR_HSERDY)
 			break;
 	}
 
-	if (!(rcc_regs->cr & STM32F2_RCC_CR_HSERDY)) {
+	if (!(STM32F2_RCC->cr & STM32F2_RCC_CR_HSERDY)) {
 		/*
 		 * Have no HSE clock
 		 */
 		goto out;
 	}
 
-	val = rcc_regs->cfgr;
+	val = STM32F2_RCC->cfgr;
 
 	/*
 	 * HCLK = SYSCLK / 1
@@ -260,7 +254,7 @@ static void clock_setup(void)
 	val &= ~(STM32F2_RCC_CFGR_PPRE1_MSK << STM32F2_RCC_CFGR_PPRE1_BIT);
 	val |= STM32F2_RCC_CFGR_PPRE1_DIV4 << STM32F2_RCC_CFGR_PPRE1_BIT;
 
-	rcc_regs->cfgr = val;
+	STM32F2_RCC->cfgr = val;
 
 # if defined(CONFIG_STM32F2_SYS_CLK_PLL)
 	/*
@@ -278,7 +272,7 @@ static void clock_setup(void)
 	       STM32F2_RCC_PLLCFGR_PLLP_BIT;
 	val |= CONFIG_STM32F2_PLL_Q << STM32F2_RCC_PLLCFGR_PLLQ_BIT;
 
-	rcc_regs->pllcfgr = val;
+	STM32F2_RCC->pllcfgr = val;
 
 	/*
 	 * Enable the main PLL, and wait until main PLL becomes ready.
@@ -286,13 +280,13 @@ static void clock_setup(void)
 	 * PLL to lock is probably not a constant. There's no timeout here in
 	 * STM lib code as well.
 	 */
-	rcc_regs->cr |= STM32F2_RCC_CR_PLLON;
-	while (rcc_regs->cr & STM32F2_RCC_CR_PLLRDY);
+	STM32F2_RCC->cr |= STM32F2_RCC_CR_PLLON;
+	while (STM32F2_RCC->cr & STM32F2_RCC_CR_PLLRDY);
 
 	/*
 	 * Select PLL as system source if it's setup OK, and HSE otherwise
 	 */
-	if (!(rcc_regs->cr & STM32F2_RCC_CR_PLLRDY))
+	if (!(STM32F2_RCC->cr & STM32F2_RCC_CR_PLLRDY))
 		val = STM32F2_RCC_CFGR_SWS_PLL;
 	else
 		val = STM32F2_RCC_CFGR_SWS_HSE;
@@ -312,10 +306,10 @@ static void clock_setup(void)
 	/*
 	 * Change system clock source, and wait (infinite!) till it done
 	 */
-	rcc_regs->cfgr &= ~(STM32F2_RCC_CFGR_SW_MSK <<
+	STM32F2_RCC->cfgr &= ~(STM32F2_RCC_CFGR_SW_MSK <<
 			    STM32F2_RCC_CFGR_SW_BIT);
-	rcc_regs->cfgr |= val << STM32F2_RCC_CFGR_SW_BIT;
-	while ((rcc_regs->cfgr & (STM32F2_RCC_CFGR_SWS_MSK <<
+	STM32F2_RCC->cfgr |= val << STM32F2_RCC_CFGR_SW_BIT;
+	while ((STM32F2_RCC->cfgr & (STM32F2_RCC_CFGR_SWS_MSK <<
 				  STM32F2_RCC_CFGR_SWS_BIT)) !=
 	       (val << STM32F2_RCC_CFGR_SWS_BIT));
 out:
@@ -331,8 +325,6 @@ void clock_init(void)
 	static u32 apbahb_presc_tbl[] = {0, 0, 0, 0, 1, 2, 3, 4,
 					 1, 2, 3, 4, 6, 7, 8, 9};
 
-	volatile struct stm32f2_rcc_regs *rcc_regs =
-		(struct stm32f2_rcc_regs *)STM32F2_RCC_BASE;
 	u32 tmp, presc, pllvco, pllp, pllm;
 
 #if !defined(CONFIG_STM32F2_SYS_CLK_HSI)
@@ -350,7 +342,7 @@ void clock_init(void)
 	/*
 	 * Get SYSCLK
 	 */
-	tmp  = rcc_regs->cfgr >> STM32F2_RCC_CFGR_SWS_BIT;
+	tmp  = STM32F2_RCC->cfgr >> STM32F2_RCC_CFGR_SWS_BIT;
 	tmp &= STM32F2_RCC_CFGR_SWS_MSK;
 	switch (tmp) {
 	case STM32F2_RCC_CFGR_SWS_HSI:
@@ -367,21 +359,21 @@ void clock_init(void)
 		 * PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
 		 * SYSCLK = PLL_VCO / PLLP
 		 */
-		pllm  = rcc_regs->pllcfgr >> STM32F2_RCC_PLLCFGR_PLLM_BIT;
+		pllm  = STM32F2_RCC->pllcfgr >> STM32F2_RCC_PLLCFGR_PLLM_BIT;
 		pllm &= STM32F2_RCC_PLLCFGR_PLLM_MSK;
 
-		if (rcc_regs->pllcfgr & STM32F2_RCC_PLLCFGR_HSESRC) {
+		if (STM32F2_RCC->pllcfgr & STM32F2_RCC_PLLCFGR_HSESRC) {
 			/* HSE used as PLL clock source */
 			tmp = CONFIG_STM32F2_HSE_HZ;
 		} else {
 			/* HSI used as PLL clock source */
 			tmp = STM32F2_HSI_HZ;
 		}
-		pllvco  = rcc_regs->pllcfgr >> STM32F2_RCC_PLLCFGR_PLLN_BIT;
+		pllvco  = STM32F2_RCC->pllcfgr >> STM32F2_RCC_PLLCFGR_PLLN_BIT;
 		pllvco &= STM32F2_RCC_PLLCFGR_PLLN_MSK;
 		pllvco *= tmp / pllm;
 
-		pllp  = rcc_regs->pllcfgr >> STM32F2_RCC_PLLCFGR_PLLP_BIT;
+		pllp  = STM32F2_RCC->pllcfgr >> STM32F2_RCC_PLLCFGR_PLLP_BIT;
 		pllp &= STM32F2_RCC_PLLCFGR_PLLP_MSK;
 		pllp  = (pllp + 1) * 2;
 
@@ -395,7 +387,7 @@ void clock_init(void)
 	/*
 	 * Get HCLK
 	 */
-	tmp  = rcc_regs->cfgr >> STM32F2_RCC_CFGR_HPRE_BIT;
+	tmp  = STM32F2_RCC->cfgr >> STM32F2_RCC_CFGR_HPRE_BIT;
 	tmp &= STM32F2_RCC_CFGR_HPRE_MSK;
 	presc = apbahb_presc_tbl[tmp];
 	clock_val[CLOCK_HCLK] = clock_val[CLOCK_SYSCLK] >> presc;
@@ -403,7 +395,7 @@ void clock_init(void)
 	/*
 	 * Get PCLK1
 	 */
-	tmp  = rcc_regs->cfgr >> STM32F2_RCC_CFGR_PPRE1_BIT;
+	tmp  = STM32F2_RCC->cfgr >> STM32F2_RCC_CFGR_PPRE1_BIT;
 	tmp &= STM32F2_RCC_CFGR_PPRE1_MSK;
 	presc = apbahb_presc_tbl[tmp];
 	clock_val[CLOCK_PCLK1] = clock_val[CLOCK_HCLK] >> presc;
@@ -411,7 +403,7 @@ void clock_init(void)
 	/*
 	 * Get PCLK2
 	 */
-	tmp  = rcc_regs->cfgr >> STM32F2_RCC_CFGR_PPRE2_BIT;
+	tmp  = STM32F2_RCC->cfgr >> STM32F2_RCC_CFGR_PPRE2_BIT;
 	tmp &= STM32F2_RCC_CFGR_PPRE2_MSK;
 	presc = apbahb_presc_tbl[tmp];
 	clock_val[CLOCK_PCLK2] = clock_val[CLOCK_HCLK] >> presc;

cpu/arm_cortexm3/stm32f2/envm.c

@@ -49,6 +49,8 @@ struct stm32f2_flash_regs {
 	u32	cr;				/* Control		      */
 	u32	optcr;				/* Option control	      */
 };
+#define STM32F2_FLASH	((volatile struct stm32f2_flash_regs *)		       \
+			 STM32F2_FLASH_BASE)
 
 /*
  * Enable instruction cache, prefetch and set the Flash wait latency
@@ -60,16 +62,12 @@ struct stm32f2_flash_regs {
  */
 void envm_config(u32 wait_states)
 {
-	volatile struct stm32f2_flash_regs	*flash_regs;
-
-	flash_regs = (struct stm32f2_flash_regs *)STM32F2_FLASH_BASE;
-
 	if (wait_states > STM32F2_FLASH_ACR_LAT_MSK)
 		wait_states = STM32F2_FLASH_ACR_LAT_MSK;
 
-	flash_regs->acr = STM32F2_FLASH_ACR_PRFTEN |
-			  STM32F2_FLASH_ACR_ICEN |
-			  (wait_states << STM32F2_FLASH_ACR_LAT_BIT);
+	STM32F2_FLASH->acr = STM32F2_FLASH_ACR_PRFTEN |
+			     STM32F2_FLASH_ACR_ICEN |
+			     (wait_states << STM32F2_FLASH_ACR_LAT_BIT);
 }
 
 /*

drivers/gpio/stm32f2_gpio.c

@@ -139,7 +139,6 @@ int stm32f2_gpio_config(struct stm32f2_gpio_dsc *dsc,
 			enum stm32f2_gpio_role role)
 {
 	volatile struct stm32f2_gpio_regs	*gpio_regs;
-	volatile struct stm32f2_rcc_regs	*rcc_regs;
 
 	u32	otype, ospeed, pupd, i;
 	int	rv;
@@ -185,13 +184,12 @@ int stm32f2_gpio_config(struct stm32f2_gpio_dsc *dsc,
 	/*
 	 * Get reg base
 	 */
-	rcc_regs  = (struct stm32f2_rcc_regs *)STM32F2_RCC_BASE;
 	gpio_regs = (struct stm32f2_gpio_regs *)io_base[dsc->port];
 
 	/*
 	 * Enable GPIO clocks
 	 */
-	rcc_regs->ahb1enr |= 1 << dsc->port;
+	STM32F2_RCC->ahb1enr |= 1 << dsc->port;
 
 	if (role != STM32F2_GPIO_ROLE_MCO) {
 		/*

drivers/net/stm32f2_eth.c

@@ -275,6 +275,8 @@ struct stm32f2_syscfg_regs {
 	u32	rsv0[2];
 	u32	cmpcr;		/* Compensation cell control		      */
 };
+#define STM32F2_SYSCFG	((volatile struct stm32f2_syscfg_regs *)	       \
+			 STM32F2_SYSCFG_BASE)
 
 /*
  * STM32F2 ETH Normal DMA buffer descriptors
@@ -777,13 +779,11 @@ static void stm_mac_address_set(struct stm_eth_dev *mac)
  */
 static int stm_mac_gpio_init(struct stm_eth_dev *mac)
 {
-	static struct stm32f2_gpio_dsc		mco_gpio = {0, 8};
-	static int				gpio_inited;
+	static struct stm32f2_gpio_dsc	mco_gpio = {0, 8};
+	static int			gpio_inited;
 
-	volatile struct stm32f2_rcc_regs	*rcc_regs;
-	volatile struct stm32f2_syscfg_regs	*syscfg_regs;
-	u32					val;
-	int					i, rv;
+	u32	val;
+	int	i, rv;
 
 	/*
 	 * Init GPIOs only once at start. Otherwise, reiniting then on
@@ -799,12 +799,9 @@ static int stm_mac_gpio_init(struct stm_eth_dev *mac)
 	}
 
 	/*
-	 * Get reg bases, enable SYSCFG clock
+	 * Enable SYSCFG clock
 	 */
-	rcc_regs = (struct stm32f2_rcc_regs *)STM32F2_RCC_BASE;
-	syscfg_regs = (struct stm32f2_syscfg_regs *)STM32F2_SYSCFG_BASE;
-
-	rcc_regs->apb2enr |= STM32F2_RXX_ENR_SYSCFG;
+	STM32F2_RCC->apb2enr |= STM32F2_RXX_ENR_SYSCFG;
 
 	/*
 	 * Configure MC0: PA8
@@ -816,7 +813,7 @@ static int stm_mac_gpio_init(struct stm_eth_dev *mac)
 	/*
 	 * Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY
 	 */
-	val  = rcc_regs->cfgr;
+	val  = STM32F2_RCC->cfgr;
 
 	val &= ~(STM32F2_RCC_CFGR_MCO1_MSK << STM32F2_RCC_CFGR_MCO1_BIT);
 	val |= STM32F2_RCC_CFGR_MCO1_HSE << STM32F2_RCC_CFGR_MCO1_BIT;
@@ -824,15 +821,15 @@ static int stm_mac_gpio_init(struct stm_eth_dev *mac)
 	val &= ~(STM32F2_RCC_CFGR_MCO1PRE_MSK << STM32F2_RCC_CFGR_MCO1PRE_BIT);
 	val |= STM32F2_RCC_CFGR_MCO1PRE_DIVNO << STM32F2_RCC_CFGR_MCO1PRE_BIT;
 
-	rcc_regs->cfgr = val;
+	STM32F2_RCC->cfgr = val;
 
 	/*
 	 * Set MII mode
 	 */
-	val = syscfg_regs->pmc;
+	val = STM32F2_SYSCFG->pmc;
 	val &= STM32F2_SYSCFG_PMC_SEL_MSK << STM32F2_SYSCFG_PMC_SEL_BIT;
 	val |= STM32F2_SYSCFG_PMC_SEL_MII << STM32F2_SYSCFG_PMC_SEL_BIT;
-	syscfg_regs->pmc = val;
+	STM32F2_SYSCFG->pmc = val;
 
 	/*
 	 * Set GPIOs Alternative function
@@ -855,7 +852,6 @@ out:
  */
 static int stm_mac_hw_init(struct stm_eth_dev *mac)
 {
-	volatile struct stm32f2_rcc_regs	*rcc_regs;
 	u32	tmp, hclk;
 	int	i, rv;
 
@@ -869,16 +865,15 @@ static int stm_mac_hw_init(struct stm_eth_dev *mac)
 	/*
 	 * Enable Ethernet clocks
 	 */
-	rcc_regs = (struct stm32f2_rcc_regs *)STM32F2_RCC_BASE;
-	rcc_regs->ahb1enr |= STM32F2_RCC_ENR_ETHMACEN   |
-			     STM32F2_RCC_ENR_ETHMACTXEN |
-			     STM32F2_RCC_ENR_ETHMACRXEN;
+	STM32F2_RCC->ahb1enr |= STM32F2_RCC_ENR_ETHMACEN   |
+				STM32F2_RCC_ENR_ETHMACTXEN |
+				STM32F2_RCC_ENR_ETHMACRXEN;
 
 	/*
 	 * Reset all MAC subsystem internal regs and logic
 	 */
-	rcc_regs->ahb1rstr |= STM32F2_RCC_AHB1RSTR_MAC;
-	rcc_regs->ahb1rstr &= ~STM32F2_RCC_AHB1RSTR_MAC;
+	STM32F2_RCC->ahb1rstr |= STM32F2_RCC_AHB1RSTR_MAC;
+	STM32F2_RCC->ahb1rstr &= ~STM32F2_RCC_AHB1RSTR_MAC;
 
 	mac->regs->dmabmr |= STM32F2_MAC_DMABMR_SR;
 	i = 0;

drivers/serial/stm32f2_usart.c

@@ -195,12 +195,11 @@ static volatile struct stm32f2_usart_regs	*usart_regs;
  */
 int serial_init(void)
 {
-	static struct stm32f2_gpio_dsc		tx_gpio = { USART_TX_IO_PORT,
-							    USART_TX_IO_PIN };
-	static struct stm32f2_gpio_dsc		rx_gpio = { USART_RX_IO_PORT,
-							    USART_RX_IO_PIN };
-	static volatile u32			 *usart_enr;
-	static volatile struct stm32f2_rcc_regs	 *rcc_regs;
+	static struct stm32f2_gpio_dsc	tx_gpio = { USART_TX_IO_PORT,
+						    USART_TX_IO_PIN };
+	static struct stm32f2_gpio_dsc	rx_gpio = { USART_RX_IO_PORT,
+						    USART_RX_IO_PIN };
+	static volatile u32		*usart_enr;
 
 	int	rv;
 
@@ -208,7 +207,6 @@ int serial_init(void)
 	 * Setup registers
 	 */
 	usart_regs = (struct stm32f2_usart_regs *)usart_base[USART_PORT];
-	rcc_regs   = (struct stm32f2_rcc_regs *)STM32F2_RCC_BASE;
 
 	usart_enr  = (u32 *)(STM32F2_RCC_BASE + rcc_enr_offset[USART_PORT]);
 

include/asm-arm/arch-stm32f2/stm32f2.h

@@ -91,6 +91,7 @@ enum clock {
  * RCC registers base
  */
 #define STM32F2_RCC_BASE		(STM32F2_AHB1PERITH_BASE + 0x3800)
+#define STM32F2_RCC	((volatile struct stm32f2_rcc_regs *)STM32F2_RCC_BASE)
 
 /******************************************************************************
  * Flexible static memory controller