Commit 2cbcf4d4 authored by Vladimir Khusainov's avatar Vladimir Khusainov
Browse files

RT92026 Further clean-up of the U-Boot code for the STM32F429 Discovery.

Got rid of the external Flash configuration to simplify
the board specific code.
parent 50320838
......@@ -87,7 +87,6 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
/* C11, FMC_NWE */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_5},
/* B3, FMC_A22 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_6},
/* B2, FMC_A21 */
......@@ -136,7 +135,7 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
/* E2, FMC_A0 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_0},
/* SDRAM only, Revision 0x2A */
/* SDRAM only */
/* M4, SDRAM_NE */
{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_2},
/* R6, SDRAM_NRAS */
......@@ -150,19 +149,6 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
/* H14, SDRAM_CLK */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_8},
#ifdef CONFIG_FSMC_NOR_PSRAM_CS1_ENABLE
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_7},
#endif
#ifdef CONFIG_FSMC_NOR_PSRAM_CS2_ENABLE
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_9},
#endif
#ifdef CONFIG_FSMC_NOR_PSRAM_CS3_ENABLE
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_10},
#endif
#ifdef CONFIG_FSMC_NOR_PSRAM_CS4_ENABLE
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_12},
#endif
};
/*
......@@ -194,52 +180,11 @@ out:
int board_init(void)
{
int rv;
int i;
char v;
rv = fmc_fsmc_setup_gpio();
if (rv)
return rv;
#if !defined(CONFIG_SYS_NO_FLASH)
/* Disable first bank */
fsmc_nor_psram_init(1, 0, 0, 0);
fsmc_nor_psram_init(3, 0, 0, 0);
fsmc_nor_psram_init(4, 0, 0, 0);
/*
* Put SDRAM in Self-refresh mode to workaround
* bug with Flash/SDRAM accessing,
* see errata 2.8.7
*/
STM32_RCC->ahb3enr |= 1;
__asm__ __volatile__ ("dsb" : : : "memory");
STM32_SDRAM_FMC->sdcr1 =
CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT;
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK;
FMC_BUSY_WAIT();
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_SELFREFRESH;
FMC_BUSY_WAIT();
udelay(60);
if ((rv = fsmc_nor_psram_init(CONFIG_SYS_FLASH_CS, CONFIG_SYS_FSMC_FLASH_BCR,
CONFIG_SYS_FSMC_FLASH_BTR,
CONFIG_SYS_FSMC_FLASH_BWTR)))
return rv;
for (i = 1; i < 0x1000000; i <<= 1) {
v = *(volatile char*)(0x64000000 + i);
v = *(volatile char*)(0x64000000 + i - 1);
nop(); nop();
nop(); nop();
nop(); nop();
}
#endif
return 0;
}
......@@ -248,8 +193,7 @@ int board_init(void)
*/
int checkboard(void)
{
printf("Board: STM-SOM Rev %s, www.emcraft.com\n",
CONFIG_SYS_BOARD_REV_STR);
printf("Board: STM32F429-DISCOVERY Rev %s\n", CONFIG_SYS_BOARD_REV_STR);
return 0;
}
......@@ -261,7 +205,6 @@ int checkboard(void)
static int dram_initialized = 0;
static inline u32 _ns2clk(u32 ns, u32 freq)
{
uint32_t tmp = freq/1000000;
......@@ -355,7 +298,6 @@ int dram_init(void)
udelay(100);
FMC_BUSY_WAIT();
#define SDRAM_MODE_BL_SHIFT 0
#define SDRAM_MODE_CAS_SHIFT 4
......@@ -394,122 +336,6 @@ int dram_init(void)
return rv;
}
/*
* STM32 Flash bug workaround.
*/
extern char _mem_ram_buf_base, _mem_ram_buf_size;
#define SOC_RAM_BUFFER_BASE (ulong)(&_mem_ram_buf_base)
#define SOC_RAM_BUFFER_SIZE (ulong)((&_mem_ram_buf_size) - 0x100)
void stop_ram(void)
{
if (!dram_initialized)
return;
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_SELFREFRESH;
FMC_BUSY_WAIT();
}
void start_ram(void)
{
if (!dram_initialized)
return;
/*
* Precharge according to chip requirement, page 12.
*/
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE;
FMC_BUSY_WAIT();
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL;
FMC_BUSY_WAIT();
udelay(60);
}
#define NOP10() do { nop(); nop(); nop(); nop(); nop(); \
nop(); nop(); nop(); nop(); nop(); \
} while(0);
u16 flash_read16(void *addr)
{
u16 value;
stop_ram();
value = __raw_readw(addr);
NOP10();
start_ram();
return value;
}
void flash_write16(u16 value, void *addr)
{
stop_ram();
__raw_writew(value, addr);
NOP10();
NOP10();
start_ram();
}
__attribute__((noinline)) void copy_one(volatile u16* src, volatile u16* dst)
{
*dst = *src;
}
u32 flash_write_buffer(void *src, void *dst, int cnt, int portwidth)
{
u32 retval = 0;
if (portwidth != FLASH_CFI_16BIT) {
retval = ERR_INVAL;
goto out;
}
memcpy((void*)SOC_RAM_BUFFER_BASE, (void*)src, cnt * portwidth);
stop_ram();
__asm__ __volatile__("": : :"memory");
src = (void*) SOC_RAM_BUFFER_BASE;
while(cnt-- > 0) {
copy_one(src, dst);
src += 2, dst += 2;
NOP10();
NOP10();
}
__asm__ __volatile__("": : :"memory");
start_ram();
out:
return retval;
}
u32 flash_check_flag(void *src, void *dst, int cnt, int portwidth)
{
u32 flag = 1;
if (portwidth != FLASH_CFI_16BIT) {
flag = 0;
goto out;
}
stop_ram();
while((cnt-- > 0) && (flag == 1)) {
flag = *(u16*)dst == 0xFFFF;
dst += 2;
}
start_ram();
out:
return flag;
}
#ifdef CONFIG_STM32_ETH
/*
* Register ethernet driver
......
......@@ -133,79 +133,29 @@
*/
#define CONFIG_SYS_MALLOC_LEN CONFIG_MEM_MALLOC_LEN
#define FSMC_NOR_PSRAM_CS_ADDR(n) \
(0x60000000 + ((n) - 1) * 0x4000000)
/*
* Configuration of the external SDRAM memory for Rev 2.A
*/
# define CONFIG_NR_DRAM_BANKS 1
# define CONFIG_SYS_RAM_SIZE (32 * 1024 * 1024)
# define CONFIG_SYS_RAM_CS 1
# define CONFIG_SYS_RAM_FREQ_DIV 2
# define CONFIG_SYS_RAM_BASE 0xC0000000
/*
* Configuration of the external Flash memory, common for both revisions
* Configuration of the external SDRAM memory
*/
#define CONFIG_SYS_FLASH_CS 2
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024)
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
#define CONFIG_SYS_RAM_BASE 0xC0000000
/* Flash is in ModeC, that means 'OE toggle on write' */
/*
* MBKEN(0) = 1, enable memory bank
* MTYP(3-2) = 0b10, NOR flash
* MWID(5-4) = 0b01, 16 bit
* FACCEN(6) = 1,
* reserved(7) = 0,
* WREN(12) = 1,
* EXTMOD(14) = 1
* No external Flash
*/
#define CONFIG_SYS_FSMC_FLASH_BCR 0x00005059
/*
* Flash timinigs are almost same for write and read.
* See Spansion memory reference manual for S29GL128S10DHI010
* tACC(MAX) = ADDSET(3-0) = 110 ns = 18.48 HCLK (on 168 MHz)
* tRC(MIN) = DATAST(15-8) = 110 ns = 18.48 HCLK (on 168 MHz)
* tNE switch = BUSTURN(19-16) = 10 ns = 2 HCLK
* ACCMODE(29-28) = 0x2 (mode C)
*/
#define CONFIG_SYS_FSMC_FLASH_BTR 0x2002120f
#define CONFIG_SYS_FSMC_FLASH_BWTR 0x2002110f
#define CONFIG_FSMC_NOR_PSRAM_CS2_ENABLE
#define CONFIG_SYS_FLASH_BANK1_BASE FSMC_NOR_PSRAM_CS_ADDR(CONFIG_SYS_FLASH_CS)
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BANK1_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
#define CONFIG_SYS_FLASH_PROTECTION 1
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_NO_FLASH
/*
* Store env in Flash memory
* Store env in embedded Flash
*/
#define CONFIG_ENV_IS_IN_ENVM
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BANK1_BASE
#define CONFIG_INFERNO 1
#define CONFIG_ENV_OVERWRITE 1
#endif
#ifdef CONFIG_ENV_IS_IN_ENVM
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_ENVM_BASE + CONFIG_SYS_ENVM_LEN - (128 * 1024))
#define CONFIG_INFERNO 1
#define CONFIG_ENV_OVERWRITE 1
#endif
/*
* Serial console configuration
......@@ -285,7 +235,6 @@
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
#define CONFIG_CMD_BUFCOPY
/*
* To save memory disable long help
......@@ -310,9 +259,6 @@
#define LOADADDR "0xC0007FC0"
#define REV_EXTRA_ENV \
"flashboot=run addip;" \
"stmbufcopy ${loadaddr} ${flashaddr} ${kernelsize};" \
"bootm ${loadaddr}\0" \
"envmboot=run addip;bootm ${envmaddr}\0" \
"update=tftp ${image};" \
"prot off ${flashaddr} +${filesize};" \
......@@ -330,7 +276,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=" LOADADDR "\0" \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
"flashaddr=64020000\0" \
"envmaddr=08020000\0" \
"ethaddr=C0:B1:3C:88:88:85\0" \
"ipaddr=172.17.4.206\0" \
......
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