Commit 300a296d authored by Yuri Tikhonov's avatar Yuri Tikhonov
Browse files

RT72064. stm32f2: move reg definitions to appropriate c-files



Previously, all these were located in stm32f2.h. As for me, that
was better: these definitions are really CPU-specific (describe
the CPU specific registers and their fields), and have no rela-
tion to driver or anything else c-code; latters just use them. So,
my opinion is that their place in stm32f2.h header, not in c-files.

The only positive thing here: is more clear stm32f2.h file.

Note, the definitions used by several files (e.g. RCC regs base, used
by clock.c and stm32f2_serial.c) I kept in stm32f2.h. The same about
C-types of register maps.
Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
parent 0a4233b7
......@@ -28,6 +28,38 @@
# error "Value of the External oscillator, CONFIG_STM32F2_HSE_HZ, is not set."
#endif
/*
* Internal oscillator value
*/
#define STM32F2_HSI_HZ 16000000
/*
* Offsets and bitmasks of some RCC regs
*/
#define STM32F2_RCC_CFGR_SWS_BIT 0
#define STM32F2_RCC_CFGR_SWS_MSK 0x000F
#define STM32F2_RCC_CFGR_HPRE_BIT 4
#define STM32F2_RCC_CFGR_HPRE_MSK 0x000F
#define STM32F2_RCC_CFGR_PPRE1_BIT 10
#define STM32F2_RCC_CFGR_PPRE1_MSK 0x0007
#define STM32F2_RCC_CFGR_PPRE2_BIT 13
#define STM32F2_RCC_CFGR_PPRE2_MSK 0x0007
#define STM32F2_RCC_PLLCFGR_PLLSRC_BIT 22
#define STM32F2_RCC_PLLCFGR_PLLSRC_MSK 0x0001
#define STM32F2_RCC_PLLCFGR_PLLM_BIT 0
#define STM32F2_RCC_PLLCFGR_PLLM_MSK 0x003F
#define STM32F2_RCC_PLLCFGR_PLLN_BIT 6
#define STM32F2_RCC_PLLCFGR_PLLN_MSK 0x01FF
#define STM32F2_RCC_PLLCFGR_PLLP_BIT 16
#define STM32F2_RCC_PLLCFGR_PLLP_MSK 0x0003
/*
* Clock values
*/
......
......@@ -71,6 +71,124 @@
# error "Bad CONFIG_STM32F2_USART_RX_IO_PIN value."
#endif
/*
* STM32F USART definitions
*/
/*
* USART registers bases
*/
#define STM32F2_USART1_BASE (STM32F2_APB2PERITH_BASE + 0x1000)
#define STM32F2_USART2_BASE (STM32F2_APB1PERITH_BASE + 0x4400)
#define STM32F2_USART3_BASE (STM32F2_APB1PERITH_BASE + 0x4800)
#define STM32F2_USART4_BASE (STM32F2_APB1PERITH_BASE + 0x4C00)
#define STM32F2_USART5_BASE (STM32F2_APB1PERITH_BASE + 0x5000)
#define STM32F2_USART6_BASE (STM32F2_APB2PERITH_BASE + 0x1400)
/*
* SR bit masks
*/
#define STM32F2_USART_SR_TXE (1 << 7) /* Transmit data reg empty */
#define STM32F2_USART_SR_RXNE (1 << 5) /* Read data reg not empty */
/*
* BRR reg fields
*/
#define STM32F2_USART_BRR_F_BIT 0 /* fraction of USARTDIV */
#define STM32F2_USART_BRR_F_MSK 0x0F
#define STM32F2_USART_BRR_M_BIT 4 /* mantissa of USARTDIV */
#define STM32F2_USART_BRR_M_MSK 0xFFF
/*
* CR1 bit masks
*/
#define STM32F2_USART_CR1_UE (1 << 13) /* USART enable */
#define STM32F2_USART_CR1_TE (1 << 3) /* Transmitter enable */
#define STM32F2_USART_CR1_RE (1 << 2) /* Receiver enable */
/*
* STM32F2 RCC USART specific definitions
*/
#define STM32F2_RCC_ENR_USART1 offsetof(struct stm32f2_rcc_regs, apb2enr)
#define STM32F2_RCC_MSK_USART1 (1 << 4)
#define STM32F2_RCC_ENR_USART2 offsetof(struct stm32f2_rcc_regs, apb1enr)
#define STM32F2_RCC_MSK_USART2 (1 << 17)
#define STM32F2_RCC_ENR_USART3 offsetof(struct stm32f2_rcc_regs, apb1enr)
#define STM32F2_RCC_MSK_USART3 (1 << 18)
#define STM32F2_RCC_ENR_USART4 offsetof(struct stm32f2_rcc_regs, apb1enr)
#define STM32F2_RCC_MSK_USART4 (1 << 19)
#define STM32F2_RCC_ENR_USART5 offsetof(struct stm32f2_rcc_regs, apb1enr)
#define STM32F2_RCC_MSK_USART5 (1 << 20)
#define STM32F2_RCC_ENR_USART6 offsetof(struct stm32f2_rcc_regs, apb2enr)
#define STM32F2_RCC_MSK_USART6 (1 << 5)
/*
* STM32F2 GPIOs
*/
/*
* GPIO registers bases
*/
#define STM32F2_GPIOA_BASE (STM32F2_AHB1PERITH_BASE + 0x0000)
#define STM32F2_GPIOB_BASE (STM32F2_AHB1PERITH_BASE + 0x0400)
#define STM32F2_GPIOC_BASE (STM32F2_AHB1PERITH_BASE + 0x0800)
#define STM32F2_GPIOD_BASE (STM32F2_AHB1PERITH_BASE + 0x0C00)
#define STM32F2_GPIOE_BASE (STM32F2_AHB1PERITH_BASE + 0x1000)
#define STM32F2_GPIOF_BASE (STM32F2_AHB1PERITH_BASE + 0x1400)
#define STM32F2_GPIOG_BASE (STM32F2_AHB1PERITH_BASE + 0x1800)
#define STM32F2_GPIOH_BASE (STM32F2_AHB1PERITH_BASE + 0x1C00)
#define STM32F2_GPIOI_BASE (STM32F2_AHB1PERITH_BASE + 0x2000)
/*
* GPIO configuration mode
*/
#define STM32F2_GPIO_MODE_IN 0x00
#define STM32F2_GPIO_MODE_OUT 0x01
#define STM32F2_GPIO_MODE_AF 0x02
#define STM32F2_GPIO_MODE_AN 0x03
/*
* GPIO output type
*/
#define STM32F2_GPIO_OTYPE_PP 0x00
#define STM32F2_GPIO_OTYPE_OD 0x01
/*
* GPIO output maximum frequency
*/
#define STM32F2_GPIO_SPEED_2M 0x00
#define STM32F2_GPIO_SPEED_25M 0x01
#define STM32F2_GPIO_SPEED_50M 0x02
#define STM32F2_GPIO_SPEED_100M 0x03
/*
* GPIO pullup, pulldown configuration
*/
#define STM32F2_GPIO_PUPD_NO 0x00
#define STM32F2_GPIO_PUPD_UP 0x01
#define STM32F2_GPIO_PUPD_DOWN 0x02
/*
* AF7 selection
*/
#define STM32F2_GPIO_AF_USART1 0x07
#define STM32F2_GPIO_AF_USART2 0x07
#define STM32F2_GPIO_AF_USART3 0x07
/*
* AF8 selection
*/
#define STM32F2_GPIO_AF_USART4 0x08
#define STM32F2_GPIO_AF_USART5 0x08
#define STM32F2_GPIO_AF_USART6 0x08
/*
* U-Boot global data to get the baudrate from
*/
DECLARE_GLOBAL_DATA_PTR;
/*
......@@ -238,9 +356,9 @@ void serial_setbrg(void)
*/
int_div = (25 * apb_clock) / (4 * gd->baudrate);
tmp = (int_div / 100) << STM32F2_USART_BRR_MANT_BIT;
tmp = (int_div / 100) << STM32F2_USART_BRR_M_BIT;
frac_div = int_div - (100 * (tmp >> 4));
tmp |= (((frac_div * 16) + 50) / 100) & STM32F2_USART_BRR_FRAC_MSK;
tmp |= (((frac_div * 16) + 50) / 100) & STM32F2_USART_BRR_F_MSK;
usart_regs->brr = tmp;
......
......@@ -58,38 +58,6 @@ struct stm32f2_usart_regs {
u16 gtpr; /* Guard time and prescaler */
};
/*
* USART registers bases
*/
#define STM32F2_USART1_BASE (STM32F2_APB2PERITH_BASE + 0x1000)
#define STM32F2_USART2_BASE (STM32F2_APB1PERITH_BASE + 0x4400)
#define STM32F2_USART3_BASE (STM32F2_APB1PERITH_BASE + 0x4800)
#define STM32F2_USART4_BASE (STM32F2_APB1PERITH_BASE + 0x4C00)
#define STM32F2_USART5_BASE (STM32F2_APB1PERITH_BASE + 0x5000)
#define STM32F2_USART6_BASE (STM32F2_APB2PERITH_BASE + 0x1400)
/*
* SR bit masks
*/
#define STM32F2_USART_SR_TXE (1 << 7) /* Transmit data reg empty */
#define STM32F2_USART_SR_RXNE (1 << 5) /* Read data reg not empty */
/*
* BRR reg fields
*/
#define STM32F2_USART_BRR_FRAC_BIT 0 /* fraction of USARTDIV */
#define STM32F2_USART_BRR_FRAC_MSK 0x0F
#define STM32F2_USART_BRR_MANT_BIT 4 /* mantissa of USARTDIV */
#define STM32F2_USART_BRR_MANT_MSK 0xFFF
/*
* CR1 bit masks
*/
#define STM32F2_USART_CR1_UE (1 << 13) /* USART enable */
#define STM32F2_USART_CR1_TE (1 << 3) /* Transmitter enable */
#define STM32F2_USART_CR1_RE (1 << 2) /* Receiver enable */
/******************************************************************************
* Reset and Clock Control
******************************************************************************/
......@@ -147,56 +115,6 @@ enum clock {
*/
#define STM32F2_RCC_BASE (STM32F2_AHB1PERITH_BASE + 0x3800)
/*
* Internal oscillator values
*/
#define STM32F2_HSI_HZ 16000000
/*
* Offsets and bitmasks of some RCC regs
*/
#define STM32F2_RCC_ENR_USART1 offsetof(struct stm32f2_rcc_regs, apb2enr)
#define STM32F2_RCC_MSK_USART1 (1 << 4)
#define STM32F2_RCC_ENR_USART2 offsetof(struct stm32f2_rcc_regs, apb1enr)
#define STM32F2_RCC_MSK_USART2 (1 << 17)
#define STM32F2_RCC_ENR_USART3 offsetof(struct stm32f2_rcc_regs, apb1enr)
#define STM32F2_RCC_MSK_USART3 (1 << 18)
#define STM32F2_RCC_ENR_USART4 offsetof(struct stm32f2_rcc_regs, apb1enr)
#define STM32F2_RCC_MSK_USART4 (1 << 19)
#define STM32F2_RCC_ENR_USART5 offsetof(struct stm32f2_rcc_regs, apb1enr)
#define STM32F2_RCC_MSK_USART5 (1 << 20)
#define STM32F2_RCC_ENR_USART6 offsetof(struct stm32f2_rcc_regs, apb2enr)
#define STM32F2_RCC_MSK_USART6 (1 << 5)
#define STM32F2_RCC_CFGR_SWS_BIT 0
#define STM32F2_RCC_CFGR_SWS_MSK 0x000F
#define STM32F2_RCC_CFGR_HPRE_BIT 4
#define STM32F2_RCC_CFGR_HPRE_MSK 0x000F
#define STM32F2_RCC_CFGR_PPRE1_BIT 10
#define STM32F2_RCC_CFGR_PPRE1_MSK 0x0007
#define STM32F2_RCC_CFGR_PPRE2_BIT 13
#define STM32F2_RCC_CFGR_PPRE2_MSK 0x0007
#define STM32F2_RCC_PLLCFGR_PLLSRC_BIT 22
#define STM32F2_RCC_PLLCFGR_PLLSRC_MSK 0x0001
#define STM32F2_RCC_PLLCFGR_PLLM_BIT 0
#define STM32F2_RCC_PLLCFGR_PLLM_MSK 0x003F
#define STM32F2_RCC_PLLCFGR_PLLN_BIT 6
#define STM32F2_RCC_PLLCFGR_PLLN_MSK 0x01FF
#define STM32F2_RCC_PLLCFGR_PLLP_BIT 16
#define STM32F2_RCC_PLLCFGR_PLLP_MSK 0x0003
/******************************************************************************
* General Purpose I/O
******************************************************************************/
......@@ -217,62 +135,6 @@ struct stm32f2_gpio_regs {
u32 afr[2]; /* GPIO alternate function */
};
/*
* GPIO registers bases
*/
#define STM32F2_GPIOA_BASE (STM32F2_AHB1PERITH_BASE + 0x0000)
#define STM32F2_GPIOB_BASE (STM32F2_AHB1PERITH_BASE + 0x0400)
#define STM32F2_GPIOC_BASE (STM32F2_AHB1PERITH_BASE + 0x0800)
#define STM32F2_GPIOD_BASE (STM32F2_AHB1PERITH_BASE + 0x0C00)
#define STM32F2_GPIOE_BASE (STM32F2_AHB1PERITH_BASE + 0x1000)
#define STM32F2_GPIOF_BASE (STM32F2_AHB1PERITH_BASE + 0x1400)
#define STM32F2_GPIOG_BASE (STM32F2_AHB1PERITH_BASE + 0x1800)
#define STM32F2_GPIOH_BASE (STM32F2_AHB1PERITH_BASE + 0x1C00)
#define STM32F2_GPIOI_BASE (STM32F2_AHB1PERITH_BASE + 0x2000)
/*
* GPIO configuration mode
*/
#define STM32F2_GPIO_MODE_IN 0x00
#define STM32F2_GPIO_MODE_OUT 0x01
#define STM32F2_GPIO_MODE_AF 0x02
#define STM32F2_GPIO_MODE_AN 0x03
/*
* GPIO output type
*/
#define STM32F2_GPIO_OTYPE_PP 0x00
#define STM32F2_GPIO_OTYPE_OD 0x01
/*
* GPIO output maximum frequency
*/
#define STM32F2_GPIO_SPEED_2M 0x00
#define STM32F2_GPIO_SPEED_25M 0x01
#define STM32F2_GPIO_SPEED_50M 0x02
#define STM32F2_GPIO_SPEED_100M 0x03
/*
* GPIO pullup, pulldown configuration
*/
#define STM32F2_GPIO_PUPD_NO 0x00
#define STM32F2_GPIO_PUPD_UP 0x01
#define STM32F2_GPIO_PUPD_DOWN 0x02
/*
* AF7 selection
*/
#define STM32F2_GPIO_AF_USART1 0x07
#define STM32F2_GPIO_AF_USART2 0x07
#define STM32F2_GPIO_AF_USART3 0x07
/*
* AF8 selection
*/
#define STM32F2_GPIO_AF_USART4 0x08
#define STM32F2_GPIO_AF_USART5 0x08
#define STM32F2_GPIO_AF_USART6 0x08
/******************************************************************************
* FIXME: get rid of this
******************************************************************************/
......
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