RT #89962: Build-time option for UART0 to use XTAL

cpu/arm_cortexm3/lpc18xx/clock.c

@@ -306,8 +306,13 @@ static void clock_setup(void)
 	/*
 	 * Set-up clocks for UARTs
 	 */
+#ifdef CONFIG_UART0_CLOCK_XTAL
+	LPC18XX_CGU->uart0_clk = LPC18XX_CGU_CLKSEL_XTAL |
+		LPC18XX_CGU_AUTOBLOCK_MSK;
+#else
 	LPC18XX_CGU->uart0_clk = LPC18XX_CGU_CLKSEL_PLL1 |
 		LPC18XX_CGU_AUTOBLOCK_MSK;
+#endif
 	LPC18XX_CGU->uart1_clk = LPC18XX_CGU_CLKSEL_PLL1 |
 		LPC18XX_CGU_AUTOBLOCK_MSK;
 	LPC18XX_CGU->uart2_clk = LPC18XX_CGU_CLKSEL_PLL1 |
@@ -407,7 +412,11 @@ void clock_init(void)
 	/*
 	 * Set UARTx base clock rate
 	 */
+#ifdef CONFIG_UART0_CLOCK_XTAL
+	clock_val[CLOCK_UART0] = CONFIG_LPC18XX_EXTOSC_RATE;
+#else
 	clock_val[CLOCK_UART0] = LPC18XX_PLL1_CLK_OUT;
+#endif
 	clock_val[CLOCK_UART1] = LPC18XX_PLL1_CLK_OUT;
 	clock_val[CLOCK_UART2] = LPC18XX_PLL1_CLK_OUT;
 	clock_val[CLOCK_UART3] = LPC18XX_PLL1_CLK_OUT;

drivers/serial/ns16550.c

@@ -31,6 +31,8 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 	com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;
 	com_port->dll = baud_divisor & 0xff;
 	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	if ((baud_divisor >> 16) & 0xff)
+		com_port->regA = (baud_divisor >> 16) & 0xff;
 	com_port->lcr = UART_LCRVAL;
 #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
 #if defined(CONFIG_APTIX)

drivers/serial/serial.c

@@ -146,6 +146,11 @@ static int calc_divisor (NS16550_t port)
 #define MODE_X_DIV 16
 #endif
 
+#ifdef CONFIG_SERIAL0_SPECIAL_BAUDRATE
+	if (port == serial_ports[0])
+		return CONFIG_SERIAL0_SPECIAL_BAUDRATE;
+#endif
+
 	/* Compute divisor value. Normally, we should simply return:
 	 *   CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
 	 * but we need to round that value by adding 0.5.