RT #86331. Added support for M2S-FG484-SOM. We expect possible hardware

changes in that tharget, thus it is supported in a separate configuration file
and the board-specific directory.

Makefile

@@ -3277,6 +3277,9 @@ lpc1850-eval_config : unconfig
 m2s-som_config :  unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 m2s-som emcraft m2s
 
+m2s-fg484-som_config :  unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 m2s-fg484-som emcraft m2s
+
 m2s-som-copy2_config :  unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 m2s-som emcraft m2s
 

board/emcraft/m2s-fg484-som/Makefile

+#
+# (C) Copyright 2010-2013
+# Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= board.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend

board/emcraft/m2s-fg484-som/board.c

+/*
+ * board/emcraft/m2s-som/board.c
+ *
+ * Board specific code the the Emcraft SmartFusion2 system-on-module (SOM).
+ *
+ * (C) Copyright 2012, 2013
+ * Emcraft Systems, <www.emcraft.com>
+ * Alexander Potashev <aspotashev@emcraft.com>
+ * Vladimir Khusainov <vlad@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/ddr.h>
+
+/*
+ * Generate DDR timings depending on the following DDR clock
+ */
+#define M2S_DDR_MHZ		(CONFIG_SYS_M2S_SYSREF / (1000 * 1000))
+
+/*
+ * Common conversion macros used for DDR cfg
+ */
+#define M2S_CLK_VAL(ns, div)	((((ns) * M2S_DDR_MHZ) / div))
+#define M2S_CLK_MOD(ns, div)	((((ns) * M2S_DDR_MHZ) % div))
+
+#define M2S_CLK_MIN(ns)		(M2S_CLK_MOD(ns,1000) ?			\
+				 M2S_CLK_VAL(ns,1000) + 1 :		\
+				 M2S_CLK_VAL(ns,1000))
+#define M2S_CLK32_MIN(ns)	(M2S_CLK_MOD(ns,32000) ?		\
+				 M2S_CLK_VAL(ns,32000) + 1 :		\
+				 M2S_CLK_VAL(ns,32000))
+#define M2S_CLK1024_MIN(ns)	(M2S_CLK_MOD(ns,1024000) ?		\
+				 M2S_CLK_VAL(ns,1024000) + 1 :		\
+				 M2S_CLK_VAL(ns,1024000))
+#define M2S_CLK_MAX(ns)		(M2S_CLK_VAL(ns,1000))
+#define M2S_CLK32_MAX(ns)	(M2S_CLK_VAL(ns,32000))
+#define M2S_CLK1024_MAX(ns)	(M2S_CLK_VAL(ns,1024000))
+
+/*
+ * MT46H32M16LFBF-6 params & timings
+ */
+#define DDR_BL			8	/* Burst length (value)		*/
+#define DDR_MR_BL		3	/* Burst length (power of 2)	*/
+#define DDR_BT			0	/* Burst type int(1)/seq(0)	*/
+
+#define DDR_CL			3	/* CAS (read) latency		*/
+#define DDR_WL			1	/* Write latency		*/
+#define DDR_tMRD		2
+#define DDR_tWTR		2
+#define DDR_tXP			1
+#define DDR_tCKE		1
+
+#define DDR_tRFC		M2S_CLK_MIN(72)
+#define DDR_tREFI		M2S_CLK32_MAX(7800)
+#define DDR_tCKE_pre		M2S_CLK1024_MIN(200000)
+#define DDR_tCKE_post		M2S_CLK1024_MIN(400)
+#define DDR_tRCD		M2S_CLK_MIN(18)
+#define DDR_tRRD		M2S_CLK_MIN(12)
+#define DDR_tRP			M2S_CLK_MIN(18)
+#define DDR_tRC			M2S_CLK_MIN(60)
+#define DDR_tRAS_max		M2S_CLK1024_MAX(70000)
+#define DDR_tRAS_min		M2S_CLK_MIN(42)
+#define DDR_tWR			M2S_CLK_MIN(15)
+
+/*
+ * There are no these timings exactly in spec, so take smth
+ */
+#define DDR_tCCD		2	/* 2-reads/writes (bank A to B)	*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: M2S-FG484-SOM Rev %s, www.emcraft.com\n",
+		CONFIG_SYS_BOARD_REV_STR);
+	return 0;
+}
+
+/*
+ * Initialize DRAM
+ */
+int dram_init (void)
+{
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+	volatile struct ddr_regs	*ddr = (void *)0x40020000;
+	u16				val;
+
+	/*
+	 * Enable access to MDDR regs
+	 */
+	M2S_SYSREG->mddr_cr = (1 << 0);
+
+	/*
+	 * No non-bufferable regions
+	 */
+	M2S_SYSREG->ddrb_nb_size_cr = 0;
+
+#if (DDR_BL == 16)
+	/*
+	 * Disable all DDR Bridge buffers
+	 * We suspect some bug in the buffering scheme, so disable
+	 * this for now
+	 */
+	M2S_SYSREG->ddrb_cr = 0;
+#endif
+
+	/*
+	 * Configure mode, and mapping:
+	 * - LPDDR1 + PHY-16 + ECC_DISABLE
+	 * - BANK:1-0,COL:9-0,ROW:12-0 <-> src[2]..
+	 */
+	ddr->ddrc.DYN_POWERDOWN_CR = (0 << REG_DDRC_POWERDOWN_EN);
+	ddr->ddrc.PWR_SAVE_1_CR = (4 << REG_DDRC_POST_SELFREF_GAP_X32_SHIFT) |
+		(0xc << REG_DDRC_POWERDOWN_TO_X32_SHIFT);
+
+	ddr->ddrc.MODE_CR = (  1 << REG_DDRC_MOBILE) |
+			    (  1 << REG_DDRC_SDRAM) |
+			    (0x1 << REG_DDRC_DATA_BUS_WIDTH);
+	ddr->ddrc.ADDR_MAP_BANK_CR  = 0x099F;
+	ddr->ddrc.ADDR_MAP_COL_1_CR = 0x3333;
+	ddr->ddrc.ADDR_MAP_COL_2_CR = 0xFFFF;
+	ddr->ddrc.ADDR_MAP_COL_3_CR = 0x3300;
+	ddr->ddrc.ADDR_MAP_ROW_1_CR = 0x7777;
+	ddr->ddrc.ADDR_MAP_ROW_2_CR = 0x0FFF;
+
+	/*
+	 * Setup timings
+	 */
+	ddr->ddrc.DYN_REFRESH_1_CR = DDR_tRFC << REG_DDRC_T_RFC_MIN;
+	ddr->ddrc.DYN_REFRESH_2_CR = (DDR_tREFI << REG_DDRC_T_RFC_NOM_X32);
+	ddr->ddrc.CKE_RSTN_CYCLES_1_CR = DDR_tCKE_pre << REG_DDRC_PRE_CKE_X1024;
+	ddr->ddrc.CKE_RSTN_CYCLES_2_CR = DDR_tCKE_post << REG_DDRC_POST_CKE_X1024;
+	ddr->ddrc.DRAM_BANK_ACT_TIMING_CR = (DDR_tRCD << REG_DDRC_T_RCD) |
+					    (DDR_tCCD << REG_DDRC_T_CCD) |
+					    (DDR_tRRD << REG_DDRC_T_RRD) |
+					    (DDR_tRP << REG_DDRC_T_RP);
+	ddr->ddrc.DRAM_BANK_TIMING_PARAM_CR = DDR_tRC << REG_DDRC_T_RC;
+	ddr->ddrc.DRAM_MR_TIMING_PARAM_CR = DDR_tMRD << REG_DDRC_T_MRD;
+	ddr->ddrc.DRAM_RAS_TIMING_CR = (DDR_tRAS_max << REG_DDRC_T_RAS_MAX) |
+				       (DDR_tRAS_min << REG_DDRC_T_RAS_MIN);
+	ddr->ddrc.DFI_RDDATA_EN_CR = DDR_CL << REG_DDRC_DFI_T_RDDATA_EN;
+
+	ddr->ddrc.DRAM_RD_WR_LATENCY_CR = (DDR_WL << REG_DDRC_WRITE_LATENCY) |
+					  (DDR_CL << REG_DDRC_READ_LATENCY);
+
+	/*
+	 * DDR Mode register values
+	 * - Burst Length, CL, and BT=Interleaved
+	 * - Drive Strength 1/2
+	 */
+	val = (DDR_CL << 4) | (DDR_BT << 3) | (DDR_MR_BL << 0);
+	ddr->ddrc.INIT_MR_CR = val;
+	ddr->ddrc.INIT_EMR_CR = 0x0020;
+	ddr->ddrc.MODE_REG_DATA_CR = val;
+	ddr->ddrc.MODE_REG_RD_WR_CR = 1 << 3;
+
+	/*
+	 * Configure BL16, and related timings
+	 */
+	ddr->ddrc.PERF_PARAM_1_CR = ((DDR_BL >> 2) << REG_DDRC_BURST_RDWR);
+	ddr->ddrc.PERF_PARAM_2_CR = (DDR_BT << REG_DDRC_BURST_MODE);
+
+	ddr->ddrc.DRAM_RD_WR_TRNARND_TIME_CR = ((DDR_CL + (DDR_BL/2) + 2 -
+						 DDR_WL) << REG_DDRC_RD2WR) |
+					       ((DDR_WL + DDR_tWTR +
+						(DDR_BL/2)) << REG_DDRC_WR2RD);
+	ddr->ddrc.DRAM_RD_WR_PRE_CR = ((DDR_WL + (DDR_BL/2) +
+					DDR_tWR) << REG_DDRC_WR2PRE) |
+				      ((DDR_BL/2) << REG_DDRC_RD2PRE);
+
+	ddr->ddrc.DRAM_T_PD_CR = (DDR_tXP << REG_DDRC_T_XP) |
+				 (DDR_tCKE << REG_DDRC_T_CKE);
+
+	/*
+	 * Queue params
+	 * FIXME: clean-up these somehow
+	 */
+	ddr->ddrc.HPR_QUEUE_PARAM_1_CR = 0x80F8;
+	ddr->ddrc.HPR_QUEUE_PARAM_2_CR = 0x0007;
+	ddr->ddrc.LPR_QUEUE_PARAM_1_CR = 0x80F8;
+	ddr->ddrc.LPR_QUEUE_PARAM_2_CR = 0x0007;
+	ddr->ddrc.WR_QUEUE_PARAM_CR    = 0x0200;
+
+	/*
+	 * PHY Registers
+	 * FIXME: clean-up these somehow
+	 */
+	ddr->phy.DYN_LOOPBACK_TEST_CR		= 0x0000;
+	ddr->phy.CTRL_SLAVE_RATIO_CR		= 0x0080;
+	ddr->phy.DATA_SLICE_IN_USE_CR		= 0x000F;
+	ddr->phy.DLL_LOCK_DIFF_CR		= 0x000B;
+
+	ddr->phy.FIFO_WE_SLAVE_RATIO_1_CR	= 0x0000;
+	ddr->phy.FIFO_WE_SLAVE_RATIO_2_CR	= 0x0000;
+	ddr->phy.FIFO_WE_SLAVE_RATIO_3_CR	= 0x0000;
+	ddr->phy.FIFO_WE_SLAVE_RATIO_4_CR	= 0x0000;
+
+	ddr->phy.LOCAL_ODT_CR			= 0x0001;
+
+	ddr->phy.RD_DQS_SLAVE_RATIO_1_CR	= 0x0040;
+	ddr->phy.RD_DQS_SLAVE_RATIO_2_CR	= 0x0401;
+	ddr->phy.RD_DQS_SLAVE_RATIO_3_CR	= 0x4010;
+
+	ddr->phy.WR_DATA_SLAVE_RATIO_1_CR	= 0x0040;
+	ddr->phy.WR_DATA_SLAVE_RATIO_2_CR	= 0x0401;
+	ddr->phy.WR_DATA_SLAVE_RATIO_3_CR	= 0x4010;
+
+	ddr->phy.WR_RD_RL_CR			= 0x0000;
+	ddr->phy.RDC_WE_TO_RE_DELAY_CR		= 0x0003;
+	ddr->phy.USE_FIXED_RE_CR		= 0x0001;
+	ddr->phy.USE_RANK0_DELAYS_CR		= 0x0001;
+	ddr->phy.DYN_CONFIG_CR			= 0x0009;
+	ddr->phy.DQ_OFFSET_1_CR			= 0x0000;
+	ddr->phy.DQ_OFFSET_2_CR			= 0x0000;
+	ddr->phy.DYN_RESET_CR			= 0x0001;
+
+	ddr->ddrc.DYN_SOFT_RESET_CR		= 0x0001;
+
+	/*
+	 * Fill in global info with description of SRAM configuration.
+	 */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
+	gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
+#endif
+
+        return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#ifdef CONFIG_M2S_ETH
+int board_eth_init(bd_t *bis)
+{
+	return m2s_eth_driver_init(bis);
+}
+#endif
+

include/configs/m2s-fg484-som.h

+/*
+ * (C) Copyright 2012,2013
+ * Emcraft Systems, <www.emcraft.com>
+ * Alexander Potashev <aspotashev@emcraft.com>
+ * Vladimir Khusainov, <vlad@emcraft.com>
+ * Yuri Tikhonov, <yur@emcraft.com>
+ * Sergei Poselenov, <sposelenov@emcraft.com>
+ *
+ * Configuration settings for Emcraft SmartFusion2 SOM board
+ * (M2S-FG484-SOM).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Disable debug messages
+ */
+#undef DEBUG
+
+/*
+ * This is an ARM Cortex-M3 CPU core
+ */
+#define CONFIG_SYS_ARMCORTEXM3
+
+/*
+ * This is the Actel SmartFusion2 (aka M2S) device
+ */
+#define CONFIG_SYS_M2S
+
+/*
+ * System frequencies are defined by Libero, with no
+ * known way (as of yet) to read them in run time. Hence,
+ * we define them as build-time constants
+ */
+#define CONFIG_SYS_M2S_SYSREF		166000000
+
+/*
+ * This is a specific revision of the board
+ */
+#define CONFIG_SYS_BOARD_REV		0x1A
+
+#if (CONFIG_SYS_BOARD_REV!=0x1A)
+#error CONFIG_SYS_BOARD_REV must be 1A
+#endif
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CONFIG_SYS_BOARD_REV_STR	"A"
+
+/*
+ * Monitor prompt
+ */
+#define CONFIG_SYS_PROMPT		"M2S-FG484-SOM> "
+
+/*
+ * We want to call the CPU specific initialization
+ */
+#define CONFIG_ARCH_CPU_INIT
+
+/*
+ * This ensures that the SoC-specific cortex_m3_soc_init() gets invoked.
+ */
+#define CONFIG_ARMCORTEXM3_SOC_INIT
+
+/*
+ * Number of clock ticks in 1 sec
+ */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Enable/disable h/w watchdog
+ */
+#undef CONFIG_HW_WATCHDOG
+
+/*
+ * No interrupts
+ */
+#undef CONFIG_USE_IRQ
+
+/*
+ * Cache configuration
+ */
+#define CONFIG_M2S_CACHE_ON
+
+/*
+ * Memory layout configuration
+ */
+#define CONFIG_MEM_NVM_BASE		0x00000000
+#define CONFIG_MEM_NVM_LEN		(256 * 1024)
+
+#if 0
+/*
+ * Define the constant below to build U-boot for running
+ * from offset 0x20000 (128KB) in eNVM. When built this way,
+ * use the following commands to test the newly built U-boot:
+ * - tftp u-boot.bin
+ * - cptf 20000 ${loadaddr} ${filesize} 0
+ * - go 20375 (or check address of _start in u-boot.map)
+ */
+#define CONFIG_MEM_NVM_UBOOT_OFF	(128 * 1024)
+#endif
+
+#define CONFIG_MEM_RAM_BASE		0x20000000
+#define CONFIG_MEM_RAM_LEN		(16 * 1024)
+#define CONFIG_MEM_RAM_BUF_LEN		(32 * 1024)
+#define CONFIG_MEM_MALLOC_LEN		(12 * 1024)
+#define CONFIG_MEM_STACK_LEN		(4 * 1024)
+
+/*
+ * malloc() pool size
+ */
+#define CONFIG_SYS_MALLOC_LEN		CONFIG_MEM_MALLOC_LEN
+
+/*
+ * Configuration of the external memory
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_RAM_BASE		0xA0000000
+#define CONFIG_SYS_RAM_SIZE		(64 * 1024 * 1024)
+
+/*
+ * Configuration of the external Flash
+ * No NOR Flash
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Configure the SPI contoler device driver
+ * FIFO Size is 64K, but leave 5 bytes for cmd[] + addr[]
+ */
+#define CONFIG_M2S_SPI			1
+#define CONFIG_SPI_MAX_XF_LEN		65530
+
+/*
+ * Configure SPI Flash
+ */
+
+#define CONFIG_SPI_FLASH		1
+#define CONFIG_SPI_FLASH_SPANSION	1
+#define CONFIG_SPI_FLASH_BUS		0
+#define CONFIG_SPI_FLASH_CS		0
+#define CONFIG_SPI_FLASH_MODE		3
+#define CONFIG_SPI_FLASH_SPEED		(CONFIG_SYS_M2S_SYSREF / 4)
+#define CONFIG_SF_DEFAULT_SPEED		CONFIG_SPI_FLASH_SPEED
+#define CONFIG_SF_DEFAULT_MODE		CONFIG_SPI_FLASH_MODE
+
+/*
+ * U-boot environment configuration
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_OFFSET		0x0
+#define CONFIG_ENV_SPI_BUS		CONFIG_SPI_FLASH_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SPI_FLASH_CS
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SPI_FLASH_SPEED
+#define CONFIG_ENV_SPI_MODE		CONFIG_SPI_FLASH_MODE
+
+#define CONFIG_INFERNO			1
+#define CONFIG_ENV_OVERWRITE		1
+
+/*
+ * Location of kernel image and Co in SPI.
+ * Linux MTD driver has no boot sectors support, so locate kernel
+ * with 64K alignment
+ */
+#define CONFIG_ENV_IMG_OFFSET		0x10000
+
+/*
+ * Serial console configuration: MSS UART1
+ */
+#define CONFIG_SYS_NS16550		1
+#undef CONFIG_NS16550_MIN_FUNCTIONS
+#define CONFIG_SYS_NS16550_SERIAL	1
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		clock_get(CLOCK_PCLK0)
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		0x40000000
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Console I/O buffer size
+ */
+#define CONFIG_SYS_CBSIZE		256
+
+/*
+ * Print buffer size
+ */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Ethernet driver configuration
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_M2S_ETH
+
+#define CONFIG_SYS_RX_ETH_BUFFER	2
+
+/*
+ * Use standard MII PHY API
+ */
+#define CONFIG_MII
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_RAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_RAM_BASE + \
+					CONFIG_SYS_RAM_SIZE)
+
+/*
+ * Needed by "loadb"
+ */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_RAM_BASE
+
+/*
+ * Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
+ * not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
+ */
+#define CONFIG_SYS_MONITOR_BASE		0x0
+
+/*
+ * Monitor is not in flash. Needs to define this to prevent
+ * U-Boot from running flash_protect() on the monitor code.
+ */
+#define CONFIG_MONITOR_IS_IN_RAM	1
+
+/*
+ * Enable all those monitor commands that are needed
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_ECHO
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_LOADS
+#undef CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_SOMTEST
+#if defined(CONFIG_SPI_FLASH)
+#define CONFIG_CMD_SF
+#endif
+
+/*
+ * To save memory disable long help
+ */
+#undef CONFIG_SYS_LONGHELP
+
+/*
+ * Max number of command args
+ */
+#define CONFIG_SYS_MAXARGS		16
+
+/*
+ * Auto-boot sequence configuration
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_HOSTNAME			m2s-fg484-som
+#define CONFIG_BOOTARGS			"m2s_platform=m2s-fg484-som "\
+					"console=ttyS0,115200 panic=10"
+#define CONFIG_BOOTCOMMAND		"run flashboot"
+
+/*
+ * Macro for the "loadaddr". The most optimal load address
+ * for the non-compressed uImage is the kernel link address
+ * (CONFIG_SYS_RAM_BASE + 0x8000) minus sizeof uImage header (0x40),
+ * so the kernel start address would be loaded just to the right
+ * place.
+ */
+#define UIMAGE_LOADADDR			0xA0007FC0
+
+/*
+ * Short-cuts to some useful commands (macros)
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"loadaddr=" MK_STR(UIMAGE_LOADADDR) "\0"		\
+	"ethaddr=C0:B1:3C:83:83:83\0"				\
+	"ipaddr=172.17.4.219\0"					\
+	"serverip=172.17.0.1\0"					\
+	"image=networking.uImage\0"				\
+	"spiaddr=" MK_STR(CONFIG_ENV_IMG_OFFSET) "\0"		\
+	"spisize=400000\0"					\