Commit 39b7844b authored by Yuri Tikhonov's avatar Yuri Tikhonov

RT #89962 K70: enable PLL0 to get 48MHz clock for USB-FS

Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
parent 427d84f4
......@@ -611,7 +611,7 @@ static void clock_fei_to_fbe(void)
KINETIS_MCG_S_CLKST_EXT_REF);
}
#ifndef KINETIS_MCGOUT_PLL1
#if defined(KINETIS_MCGOUT_PLL0) || !defined(KINETIS_MCGOUT_PLL1)
static void clock_setup_pll0(void)
{
/*
......@@ -649,7 +649,7 @@ static void clock_setup_pll0(void)
*/
while (!(KINETIS_MCG->status & KINETIS_MCG_S_LOCK_MSK));
}
#endif /* !KINETIS_MCGOUT_PLL1 */
#endif /* KINETIS_MCGOUT_PLL0 */
#if defined(KINETIS_MCGOUT_PLL1) || \
(defined(CONFIG_KINETIS_DDR) && !defined(CONFIG_KINETIS_DDR_SYNC))
......@@ -701,17 +701,21 @@ static void clock_fbe_to_pbe(void)
/*
* Configure the PLL that we will use for the MCGOUTCLK
*/
#ifdef KINETIS_MCGOUT_PLL1
#if defined(KINETIS_MCGOUT_PLL1)
clock_setup_pll1();
#endif
#if defined(KINETIS_MCGOUT_PLL0)
clock_setup_pll0();
#endif
#if defined(KINETIS_MCGOUT_PLL1)
/* Select PLL1 output as the MCG source clock */
KINETIS_MCG->c11 |= KINETIS_MCG_C11_PLLCS_MSK;
#else
clock_setup_pll0();
/* Select PLL0 output as the MCG source clock */
KINETIS_MCG->c11 &= ~KINETIS_MCG_C11_PLLCS_MSK;
#endif /* KINETIS_MCGOUT_PLL1 */
#endif
/*
* Switch to the PBE mode
......
......@@ -192,8 +192,8 @@
/* PLL input divider: 12/1 = 12 MHz */
#define KINETIS_PLL_PRDIV 1
/* PLL multiplier: 12*25/2 = 150 MHz */
#define KINETIS_PLL_VDIV 25
/* PLL multiplier: 12*16/2 = 96 MHz */
#define KINETIS_PLL_VDIV 16
/* PLL1 input divider: 12/1 = 12 MHz */
#define KINETIS_PLL1_PRDIV 1
/* PLL1 multiplier: 12*25/2 = 150 MHz */
......@@ -203,6 +203,10 @@
/* Use PLL1 for MCGOUT (required for synchronous mode of the DDR controller) */
#define KINETIS_MCGOUT_PLL1
/* Use PLL0 (required for USB-FS) */
#define KINETIS_MCGOUT_PLL0
/*
* Number of clock ticks in 1 sec
*/
......
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