Commit 41ef7ac1 authored by Yuri Tikhonov's avatar Yuri Tikhonov
Browse files

stm32 eth: don't configure MCO1 (use external clock for PHY)


Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
parent 268cf2a2
...@@ -155,23 +155,6 @@ ...@@ -155,23 +155,6 @@
/* /*
* STM32 RCC MAC specific definitions * STM32 RCC MAC specific definitions
*/ */
#define STM32_RCC_CFGR_MCO1_BIT 21 /* MC clock output 1 */
#define STM32_RCC_CFGR_MCO1_MSK 0x3
#define STM32_RCC_CFGR_MCO1_HSI 0x0 /* Clock source */
#define STM32_RCC_CFGR_MCO1_LSE 0x1
#define STM32_RCC_CFGR_MCO1_HSE 0x2
#define STM32_RCC_CFGR_MCO1_PLL 0x3
#define STM32_RCC_CFGR_MCO1PRE_BIT 24 /* MCO1 prescaler */
#define STM32_RCC_CFGR_MCO1PRE_MSK 0x7
#define STM32_RCC_CFGR_MCO1PRE_DIVNO 0x0 /* Division by X */
#define STM32_RCC_CFGR_MCO1PRE_DIV2 0x4
#define STM32_RCC_CFGR_MCO1PRE_DIV3 0x5
#define STM32_RCC_CFGR_MCO1PRE_DIV4 0x6
#define STM32_RCC_CFGR_MCO1PRE_DIV5 0x7
#define STM32_RCC_AHB1RSTR_MAC (1 << 25) /* Reset MAC */ #define STM32_RCC_AHB1RSTR_MAC (1 << 25) /* Reset MAC */
#define STM32_RXX_ENR_SYSCFG (1 << 14) /* SYSCFG clock */ #define STM32_RXX_ENR_SYSCFG (1 << 14) /* SYSCFG clock */
...@@ -333,8 +316,6 @@ struct stm_mac_gpio { ...@@ -333,8 +316,6 @@ struct stm_mac_gpio {
/* /*
* Ethernet GPIOs: * Ethernet GPIOs:
* *
* MCO ------------------------------> PA8
*
* ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1 * ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1
* ETH_MDIO -------------------------> PA2 * ETH_MDIO -------------------------> PA2
* ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7 * ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7
...@@ -773,11 +754,10 @@ static void stm_mac_address_set(struct stm_eth_dev *mac) ...@@ -773,11 +754,10 @@ static void stm_mac_address_set(struct stm_eth_dev *mac)
*/ */
static int stm_mac_gpio_init(struct stm_eth_dev *mac) static int stm_mac_gpio_init(struct stm_eth_dev *mac)
{ {
static struct stm32f2_gpio_dsc mco_gpio = {0, 8}; static int gpio_inited;
static int gpio_inited;
u32 val; u32 val;
int i, rv; int i, rv;
/* /*
* Init GPIOs only once at start. Otherwise, reiniting then on * Init GPIOs only once at start. Otherwise, reiniting then on
...@@ -797,26 +777,6 @@ static int stm_mac_gpio_init(struct stm_eth_dev *mac) ...@@ -797,26 +777,6 @@ static int stm_mac_gpio_init(struct stm_eth_dev *mac)
*/ */
STM32_RCC->apb2enr |= STM32_RXX_ENR_SYSCFG; STM32_RCC->apb2enr |= STM32_RXX_ENR_SYSCFG;
/*
* Configure MC0: PA8
*/
rv = stm32f2_gpio_config(&mco_gpio, STM32F2_GPIO_ROLE_MCO);
if (rv != 0)
goto out;
/*
* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY
*/
val = STM32_RCC->cfgr;
val &= ~(STM32_RCC_CFGR_MCO1_MSK << STM32_RCC_CFGR_MCO1_BIT);
val |= STM32_RCC_CFGR_MCO1_HSE << STM32_RCC_CFGR_MCO1_BIT;
val &= ~(STM32_RCC_CFGR_MCO1PRE_MSK << STM32_RCC_CFGR_MCO1PRE_BIT);
val |= STM32_RCC_CFGR_MCO1PRE_DIVNO << STM32_RCC_CFGR_MCO1PRE_BIT;
STM32_RCC->cfgr = val;
/* /*
* Set MII mode * Set MII mode
*/ */
......
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