RT73025. ea-lpc1788: configure MPU to allow code execution in SDRAM

This is required for any code execution (including the Linux kernel) in
the external RAM on LPC178x/7x.

cpu/arm_cortexm3/cpu.c

@@ -129,3 +129,26 @@ u8 cortex_m3_irq_vec_get(void)
 {
 	return CM3_SCB_REGS->icsr & CM3_ICSR_VECTACT_MSK;
 }
+
+/*
+ * Add a custom MPU region
+ *
+ * region = Region Number
+ * address = Region Base Address
+ * attr = Region Attributes and Size
+ */
+void cortex_m3_mpu_add_region(u32 region, u32 address, u32 attr)
+{
+	CM3_MPU_REGS->rnr = region;
+	CM3_MPU_REGS->rbar = address;
+	CM3_MPU_REGS->rasr = attr;
+}
+
+/*
+ * Enable or disable configurable MPU memory regions
+ */
+void cortex_m3_mpu_enable(int enable)
+{
+	CM3_MPU_REGS->ctrl =
+		enable ? (CM3_MPU_CTRL_EN_MSK | CM3_MPU_CTRL_HFNMI_EN_MSK) : 0;
+}

cpu/arm_cortexm3/lpc178x/soc.c

@@ -55,5 +55,18 @@ void cortex_m3_soc_init(void)
 	 */
 	lpc178x_periph_enable(uart_pconp_mask[CONFIG_LPC178X_UART_PORT], 1);
 #endif
+
+	/*
+	 * Configure the memory protection unit (MPU) to allow full access to
+	 * the whole 4GB address space.
+	 *
+	 * This is required, because in the default configuration code
+	 * execution is not permitted at the addresses above 0xA0000000
+	 * (including SDRAM.)
+	 */
+	cortex_m3_mpu_add_region(0, 0x00000000,
+		CM3_MPU_RASR_AP_RW_RW | CM3_MPU_RASR_SIZE_4GB |
+		CM3_MPU_RASR_EN);
+	cortex_m3_mpu_enable(1);
 }
 #endif

include/asm-arm/arch-cortexm3/hardware.h

@@ -48,6 +48,46 @@ struct cm3_scb {
 #define CM3_ICSR_VECTACT_MSK		0xFF
 
 
+/* MPU Base Address */
+#define CM3_MPU_BASE			0xE000ED90
+struct cm3_mpu {
+	uint32_t type;			/* Type Register */
+	uint32_t ctrl;			/* Control Register */
+	uint32_t rnr;			/* Region Number Register */
+	uint32_t rbar;			/* Region Base Address Register */
+	uint32_t rasr;			/* Region Attribute and Size Register */
+};
+#define CM3_MPU_REGS		((volatile struct cm3_mpu *)CM3_MPU_BASE)
+
+/*
+ * MPU Region Base Address Register
+ */
+/*
+ * MPU Region Attribute and Size Register
+ */
+/* Region enable bit */
+#define CM3_MPU_RASR_EN			(1 << 0)
+/*
+ * Region size field
+ */
+#define CM3_MPU_RASR_SIZE_BITS		1
+#define CM3_MPU_RASR_SIZE_4GB		(31 << CM3_MPU_RASR_SIZE_BITS)
+/*
+ * Access permission field
+ */
+/* Full access for both privileged and unprivileged software */
+#define CM3_MPU_RASR_AP_RW_RW		(3 << 24)
+
+/*
+ * MPU Control register
+ */
+/*
+ * Enables the operation of MPU during hard fault, NMI, and
+ * FAULTMASK handlers
+ */
+#define CM3_MPU_CTRL_EN_MSK		(1 << 0)
+#define CM3_MPU_CTRL_HFNMI_EN_MSK	(1 << 1)
+
 /* SysTick Base Address */
 #define CM3_SYSTICK_BASE		0xE000E010
 struct cm3_systick {
@@ -65,4 +105,7 @@ struct cm3_systick {
 
 u8 cortex_m3_irq_vec_get(void);
 
+void cortex_m3_mpu_add_region(u32 region, u32 address, u32 attr);
+void cortex_m3_mpu_enable(int enable);
+
 #endif