Commit 4f1f120f authored by Yuri Tikhonov's avatar Yuri Tikhonov
Browse files

RT72064. stm32f2 clock: move Flash related stuff to envm.c


Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
parent d0498cbc
......@@ -23,16 +23,24 @@
/*
* Initialize the eNVM interface
*/
extern void envm_init(void);
void envm_init(void);
/*
* Write a data buffer to eNVM.
* Note that we need for this function to reside in RAM since it
* will be used to self-upgrade U-boot in eNMV.
*/
extern unsigned int
unsigned int
__attribute__((section(".ramcode")))
__attribute__ ((long_call))
envm_write(unsigned int offset, void * buf, unsigned int size);
#if defined(CONFIG_SYS_STM32F2)
/*
* Enable instruction cache, prefetch and set the Flash wait latency
* according to the clock configuration used (HCLK value).
*/
void envm_config(u32 wait_states);
#endif /* CONFIG_SYS_STM32F2 */
#endif /* __ENVM_H__ */
......@@ -23,6 +23,7 @@
#include <asm/arch/stm32f2.h>
#include "clock.h"
#include "envm.h"
/*
* STM32F2 Clock configuration is set by the number of CONFIG options.
......@@ -199,60 +200,16 @@
#define STM32F2_RCC_PLLCFGR_PLLQ_BIT 24 /* Div factor for USB,SDIO,.. */
#define STM32F2_RCC_PLLCFGR_PLLQ_MSK 0xF
/*
* Flash registers base
*/
#define STM32F2_FLASH_BASE (STM32F2_AHB1PERITH_BASE + 0x3C00)
/*
* Flash ACR definitions
*/
#define STM32F2_FLASH_ACR_LAT_BIT 0 /* Latency */
#define STM32F2_FLASH_ACR_LAT_MSK 0x3
#define STM32F2_FLASH_ACR_PRFTEN (1 << 8) /* Prefetch enable */
#define STM32F2_FLASH_ACR_ICEN (1 << 9) /* Instruction cache enable*/
/*
* Timeouts (in cycles)
*/
#define STM32F2_HSE_STARTUP_TIMEOUT 0x0500
/*
* Flash register map
*/
struct stm32f2_flash_regs {
u32 acr; /* Access control */
u32 keyr; /* Key */
u32 optkeyr; /* Option key */
u32 sr; /* Status */
u32 cr; /* Control */
u32 optcr; /* Option control */
};
/*
* Clock values
*/
static u32 clock_val[CLOCK_END];
/*
* Enable instruction cache, prefetch and set the Flash wait latency
* according to the clock configuration used (HCLK value).
* We _must_ do this before changing System clock source (or will crash on
* fetching instructions of while() wait cycle).
* In case of HSI clock - no Sys clock change happens, but, for consistency,
* we configure Flash this way as well.
*/
static void flash_setup(void)
{
volatile struct stm32f2_flash_regs *flash_regs;
flash_regs = (struct stm32f2_flash_regs *)STM32F2_FLASH_BASE;
flash_regs->acr = STM32F2_FLASH_ACR_PRFTEN |
STM32F2_FLASH_ACR_ICEN |
(STM32F2_FLASH_WS << STM32F2_FLASH_ACR_LAT_BIT);
}
#if !defined(CONFIG_STM32F2_SYS_CLK_HSI)
/*
* Set-up clock configuration.
......@@ -351,7 +308,7 @@ static void clock_setup(void)
* Configure Flash prefetch, Instruction cache, and wait
* latency.
*/
flash_setup();
envm_config(STM32F2_FLASH_WS);
/*
* Change system clock source, and wait (infinite!) till it done
......@@ -388,7 +345,7 @@ void clock_init(void)
/*
* For consistency with !HSI configs, enable prefetch and cache
*/
flash_setup();
envm_config(STM32F2_FLASH_WS);
#endif
/*
......
......@@ -20,9 +20,58 @@
*/
#include <common.h>
#include <asm/arch/stm32f2.h>
#include "envm.h"
/*
* Flash registers base
*/
#define STM32F2_FLASH_BASE (STM32F2_AHB1PERITH_BASE + 0x3C00)
/*
* Flash ACR definitions
*/
#define STM32F2_FLASH_ACR_LAT_BIT 0 /* Latency */
#define STM32F2_FLASH_ACR_LAT_MSK 0x3
#define STM32F2_FLASH_ACR_PRFTEN (1 << 8) /* Prefetch enable */
#define STM32F2_FLASH_ACR_ICEN (1 << 9) /* Instruction cache enable*/
/*
* Flash register map
*/
struct stm32f2_flash_regs {
u32 acr; /* Access control */
u32 keyr; /* Key */
u32 optkeyr; /* Option key */
u32 sr; /* Status */
u32 cr; /* Control */
u32 optcr; /* Option control */
};
/*
* Enable instruction cache, prefetch and set the Flash wait latency
* according to the clock configuration used (HCLK value).
* We _must_ do this before changing System clock source (or will crash on
* fetching instructions of while() wait cycle).
* In case of HSI clock - no Sys clock change happens, but, for consistency,
* we configure Flash this way as well.
*/
void envm_config(u32 wait_states)
{
volatile struct stm32f2_flash_regs *flash_regs;
flash_regs = (struct stm32f2_flash_regs *)STM32F2_FLASH_BASE;
if (wait_states > STM32F2_FLASH_ACR_LAT_MSK)
wait_states = STM32F2_FLASH_ACR_LAT_MSK;
flash_regs->acr = STM32F2_FLASH_ACR_PRFTEN |
STM32F2_FLASH_ACR_ICEN |
(wait_states << STM32F2_FLASH_ACR_LAT_BIT);
}
/*
* Initialize internal Flash interface
*/
......
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