Commit 50320838 authored by Vladimir Khusainov's avatar Vladimir Khusainov
Browse files

RT92026 Ported the U-Boot port for the STM32F429 Discover to

the STM32F429 SOM (the Rev 2A STM32F4 SOM). No port to the Discovery yet!
parent beae540c
......@@ -33,25 +33,13 @@
#include <asm/arch/stm32.h>
#include <asm/arch/stm32f2_gpio.h>
#if CONFIG_SYS_BOARD_REV == 0x2A
# include <asm/arch/fmc.h>
# include <flash.h>
# include <asm/io.h>
# include <asm/system.h>
#endif
#include <asm/arch/fmc.h>
#include <flash.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/fsmc.h>
#if CONFIG_SYS_BOARD_REV == 0x1A && (CONFIG_NR_DRAM_BANKS > 0)
/*
* Check if RAM configured
*/
# if !defined(CONFIG_SYS_RAM_CS) || !defined(CONFIG_SYS_FSMC_PSRAM_BCR) || \
!defined(CONFIG_SYS_FSMC_PSRAM_BTR)
# error "Incorrect PSRAM FSMC configuration."
# endif
#endif /* CONFIG_NR_DRAM_BANKS */
DECLARE_GLOBAL_DATA_PTR;
static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
......@@ -148,7 +136,6 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
/* E2, FMC_A0 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_0},
#if CONFIG_SYS_BOARD_REV == 0x2A
/* SDRAM only, Revision 0x2A */
/* M4, SDRAM_NE */
{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_2},
......@@ -163,19 +150,6 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
/* H14, SDRAM_CLK */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_8},
#endif /* CONFIG_SYS_BOARD_REV == 0x2A */
#if CONFIG_SYS_BOARD_REV == 0x1A
/* PSRAM only */
/* B11, FMC_NWAIT */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_6},
/* A2, FMC_CRE */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_2},
/* B5, FMC_NL */
{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_7},
/* D11, FMC_CLK */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_3},
#endif /* CONFIG_SYS_BOARD_REV == 0x1A */
#ifdef CONFIG_FSMC_NOR_PSRAM_CS1_ENABLE
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_7},
......@@ -220,10 +194,8 @@ out:
int board_init(void)
{
int rv;
#if CONFIG_SYS_BOARD_REV == 0x2A
int i;
char v;
#endif
rv = fmc_fsmc_setup_gpio();
if (rv)
......@@ -231,7 +203,6 @@ int board_init(void)
#if !defined(CONFIG_SYS_NO_FLASH)
#if CONFIG_SYS_BOARD_REV == 0x2A
/* Disable first bank */
fsmc_nor_psram_init(1, 0, 0, 0);
fsmc_nor_psram_init(3, 0, 0, 0);
......@@ -254,14 +225,12 @@ int board_init(void)
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_SELFREFRESH;
FMC_BUSY_WAIT();
udelay(60);
#endif
if ((rv = fsmc_nor_psram_init(CONFIG_SYS_FLASH_CS, CONFIG_SYS_FSMC_FLASH_BCR,
CONFIG_SYS_FSMC_FLASH_BTR,
CONFIG_SYS_FSMC_FLASH_BWTR)))
return rv;
#if CONFIG_SYS_BOARD_REV == 0x2A
for (i = 1; i < 0x1000000; i <<= 1) {
v = *(volatile char*)(0x64000000 + i);
v = *(volatile char*)(0x64000000 + i - 1);
......@@ -269,7 +238,6 @@ int board_init(void)
nop(); nop();
nop(); nop();
}
#endif
#endif
return 0;
......@@ -286,94 +254,6 @@ int checkboard(void)
return 0;
}
#if CONFIG_SYS_BOARD_REV == 0x1A
/*
* Setup external RAM.
*/
int dram_init(void)
{
static struct stm32f2_gpio_dsc ctrl_gpio = {STM32F2_GPIO_PORT_I,
STM32F2_GPIO_PIN_9};
int rv = 0;
rv = fsmc_nor_psram_init(CONFIG_SYS_RAM_CS,
CONFIG_SYS_FSMC_PSRAM_BCR,
CONFIG_SYS_FSMC_PSRAM_BTR,
#ifdef CONFIG_SYS_FSMC_PSRAM_BWTR
CONFIG_SYS_FSMC_PSRAM_BWTR
#else
(u32)-1
#endif
);
if (rv != 0)
goto out;
rv = stm32f2_gpio_config(&ctrl_gpio, STM32F2_GPIO_ROLE_GPOUT);
if (rv != 0)
goto out;
# if defined(CONFIG_SYS_RAM_BURST)
/*
* FIXME: all this hardcoded stuff.
*/
/* Step.2 */
stm32f2_gpout_set(&ctrl_gpio, 1);
/* Step.3 */
*(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x0010223E) = 0;
/* Step.4-5 */
stm32f2_gpout_set(&ctrl_gpio, 0);
/* Step.6 */
fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115,
0x0010FFFF, -1);
/* Step.7 */
rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x000000);
/* Step.8 */
fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00005059,
0x10000702, 0x10000602);
/* Step.9 */
stm32f2_gpout_set(&ctrl_gpio, 1);
/* Step.10 */
*(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x0110223E) = 0;
/* Step.11 */
stm32f2_gpout_set(&ctrl_gpio, 0);
/* Step.12 */
fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115,
0x0010FFFF, -1);
/* Step.13 */
rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x01000000);
# else
/*
* Switch PSRAM in the Asyncronous Read/Write Mode
*/
stm32f2_gpout_set(&ctrl_gpio, 0);
# endif /* CONFIG_SYS_RAM_BURST */
/*
* Fill in global info with description of SRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
rv = 0;
out:
return rv;
}
#endif /* CONFIG_SYS_BOARD_REV == 0x1A */
#if CONFIG_SYS_BOARD_REV == 0x2A
/*
* STM32 RCC FMC specific definitions
*/
......@@ -630,9 +510,6 @@ out:
return flag;
}
#endif /* CONFIG_SYS_BOARD_REV == 0x2A */
#ifdef CONFIG_STM32_ETH
/*
* Register ethernet driver
......
......@@ -29,10 +29,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#if !defined(CONFIG_SYS_BOARD_REV)
#define CONFIG_SYS_BOARD_REV 0x1A
#endif
/*
* Disable debug messages
*/
......@@ -62,20 +58,12 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#if CONFIG_SYS_BOARD_REV == 0x2A
# define CONFIG_SYS_BOARD_REV_STR "Rev 2.A"
#elif CONFIG_SYS_BOARD_REV == 0x1A
# define CONFIG_SYS_BOARD_REV_STR "Rev 1.A"
#endif
#define CONFIG_SYS_BOARD_REV_STR "Rev 1.A"
/*
* Monitor prompt
*/
#if CONFIG_SYS_BOARD_REV == 0x2A
# define CONFIG_SYS_PROMPT "STM32F4X9-SOM> "
#elif CONFIG_SYS_BOARD_REV == 0x1A
# define CONFIG_SYS_PROMPT "STM32F429> "
#endif
#define CONFIG_SYS_PROMPT "STM32F429-DISCO> "
/*
* We want to call the CPU specific initialization
......@@ -148,8 +136,6 @@
#define FSMC_NOR_PSRAM_CS_ADDR(n) \
(0x60000000 + ((n) - 1) * 0x4000000)
#if CONFIG_SYS_BOARD_REV == 0x2A
/*
* Configuration of the external SDRAM memory for Rev 2.A
*/
......@@ -159,25 +145,6 @@
# define CONFIG_SYS_RAM_FREQ_DIV 2
# define CONFIG_SYS_RAM_BASE 0xC0000000
#elif CONFIG_SYS_BOARD_REV == 0x1A
/*
* Configuration of the external PSRAM memory for Rev 1.A
*/
# define CONFIG_NR_DRAM_BANKS 1
# define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024)
# define CONFIG_SYS_RAM_CS 1
# define CONFIG_SYS_RAM_BURST
# define CONFIG_SYS_FSMC_PSRAM_BCR 0x00005059
# define CONFIG_SYS_FSMC_PSRAM_BTR 0x10000904
# define CONFIG_SYS_FSMC_PSRAM_BWTR 0x10000804
# define CONFIG_FSMC_NOR_PSRAM_CS1_ENABLE
# define CONFIG_SYS_RAM_BASE FSMC_NOR_PSRAM_CS_ADDR(CONFIG_SYS_RAM_CS)
#endif /* CONFIG_SYS_BOARD_REV is 1A */
/*
* Configuration of the external Flash memory, common for both revisions
*/
......@@ -218,14 +185,12 @@
#define CONFIG_SYS_FLASH_PROTECTION 1
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#if CONFIG_SYS_BOARD_REV == 0x2A
# define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#endif
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
/*
* Store env in Flash memory
*/
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_IS_IN_ENVM
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE (4 * 1024)
......@@ -246,31 +211,11 @@
* Serial console configuration
*/
#define CONFIG_STM32_USART_CONSOLE
#if CONFIG_SYS_BOARD_REV == 0x2A
/* Rev 2A console: USART1, TX PB.6, RX PA.10 */
# define CONFIG_STM32_USART_PORT 1 /* USART1 */
# define CONFIG_STM32_USART_TX_IO_PORT 1 /* PORTB */
# define CONFIG_STM32_USART_TX_IO_PIN 6 /* GPIO6 */
# define CONFIG_STM32_USART_RX_IO_PORT 0 /* PORTA */
# define CONFIG_STM32_USART_RX_IO_PIN 10 /* GPIO10 */
#elif CONFIG_SYS_BOARD_REV == 0x1A
/* Rev 1A console: USART3, TX PC.10, RX PC.11 */
# define CONFIG_STM32_USART_PORT 3 /* USART3 */
# define CONFIG_STM32_USART_TX_IO_PORT 2 /* PORTC */
# define CONFIG_STM32_USART_TX_IO_PIN 10 /* GPIO10 */
# define CONFIG_STM32_USART_RX_IO_PORT 2 /* PORTC */
# define CONFIG_STM32_USART_RX_IO_PIN 11 /* GPIO11 */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
......@@ -340,11 +285,7 @@
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
#if CONFIG_SYS_BOARD_REV == 0x2A
/* For loading from flash into memory */
# define CONFIG_CMD_BUFCOPY
#endif
#define CONFIG_CMD_BUFCOPY
/*
* To save memory disable long help
......@@ -363,18 +304,16 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTCOMMAND "run flashboot"
#if CONFIG_SYS_BOARD_REV == 0x2A
/* Rev 2.A boot args and env */
# define CONFIG_HOSTNAME stm32f4x9-som
# define CONFIG_BOOTARGS "stm32_platform=stm32f4x9-som "\
#define CONFIG_HOSTNAME stm32f4x9-som
#define CONFIG_BOOTARGS "stm32_platform=stm32f4x9-som "\
"console=ttyS0,115200 panic=10"
#define LOADADDR "0xC0007FC0"
# define LOADADDR "0xC0007FC0"
# define REV_EXTRA_ENV \
#define REV_EXTRA_ENV \
"flashboot=run addip;" \
"stmbufcopy ${loadaddr} ${flashaddr} ${kernelsize};" \
"bootm ${loadaddr}\0" \
"envmboot=run addip;bootm ${envmaddr}\0" \
"update=tftp ${image};" \
"prot off ${flashaddr} +${filesize};" \
"era ${flashaddr} +${filesize};" \
......@@ -383,23 +322,6 @@
"setenv filesize; setenv fileaddr;" \
"saveenv\0"
#elif CONFIG_SYS_BOARD_REV == 0x1A
/* Rev 1.A boot args and env */
# define CONFIG_HOSTNAME stm-som
# define CONFIG_BOOTARGS "stm32_platform=stm-som "\
"console=ttyS2,115200 panic=10"
# define LOADADDR "0x60000000"
# define REV_EXTRA_ENV \
"flashboot=run addip;bootm ${flashaddr}\0" \
"envmboot=run addip;bootm ${envmaddr}\0" \
"update=tftp ${image};" \
"prot off ${flashaddr} +${filesize};" \
"era ${flashaddr} +${filesize};" \
"cp.b ${loadaddr} ${flashaddr} ${filesize}\0"
#endif
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
......@@ -413,7 +335,7 @@
"ethaddr=C0:B1:3C:88:88:85\0" \
"ipaddr=172.17.4.206\0" \
"serverip=172.17.0.1\0" \
"image=stm32f4x9/uImage\0" \
"image=stm32f429/uImage\0" \
"stdin=serial\0" \
"netboot=tftp ${image};run addip;bootm\0" \
REV_EXTRA_ENV
......
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