RT #109267. STM32F7-DISCO: configure clocks

Instead of the STM32F7-SOM board, the STM32F7-DISCO board uses external
clock source.

cpu/arm_cortexm3/stm32/clock.c

@@ -153,6 +153,7 @@
  */
 #define STM32_RCC_CR_HSEON		(1 << 16) /* HSE clock enable	      */
 #define STM32_RCC_CR_HSERDY		(1 << 17) /* HSE clock ready	      */
+#define STM32_RCC_CR_HSEBYP		(1 << 18) /* HSE clock bypass	      */
 #define STM32_RCC_CR_PLLON		(1 << 24) /* PLL clock enable	      */
 #define STM32_RCC_CR_PLLRDY		(1 << 25) /* PLL clock ready	      */
 #define STM32_RCC_CR_PLLSAION		(1 << 28) /* PLLSAI enable	      */
@@ -329,7 +330,13 @@ static void clock_setup(void)
 	/*
 	 * Enable HSE, and wait while it becomes ready
 	 */
+#ifdef CONFIG_SYS_STM32F7_DISCO
+	STM32_RCC->cr &= ~STM32_RCC_CR_HSEON;
+	STM32_RCC->cr |= STM32_RCC_CR_HSEBYP;
+#else
 	STM32_RCC->cr |= STM32_RCC_CR_HSEON;
+#endif
+
 	for (i = 0; i < STM32_HSE_STARTUP_TIMEOUT; i++) {
 		if (STM32_RCC->cr & STM32_RCC_CR_HSERDY)
 			break;

include/configs/stm32f746-discovery.h

@@ -48,6 +48,7 @@
  */
 #define CONFIG_SYS_STM32
 #define CONFIG_SYS_STM32F7
+#define CONFIG_SYS_STM32F7_DISCO
 
 /*
  * Enable GPIO driver
@@ -80,9 +81,9 @@
  */
 #define CONFIG_STM32_SYS_CLK_PLL
 #define CONFIG_STM32_PLL_SRC_HSE
-#define CONFIG_STM32_HSE_HZ		12000000	/* 12 MHz */
-#define CONFIG_STM32_PLL_M		12
-#define CONFIG_STM32_PLL_N		400
+#define CONFIG_STM32_HSE_HZ		25000000	/* 25 MHz */
+#define CONFIG_STM32_PLL_M		25
+#define CONFIG_STM32_PLL_N		384
 #define CONFIG_STM32_PLL_P		2
 #define CONFIG_STM32_PLL_Q		8