RT106081: U-Boot STM32F7: create non-cacheable 'dmamem' MPU region

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

cpu/arm_cortexm3/stm32/soc.c

@@ -128,6 +128,10 @@ static void stm32f7_mpu_config(void)
 #endif
 		0 <<  8 | 24 <<  1 | 1 <<  0);
 
+	/*
+	 * !!! NOTE: MPU region [2] is set in arch_preboot_os() !!!
+	 */
+
 	/*
 	 * We don't enable cache for SRAM because some device drivers
 	 * put buffer descriptors and DMA buffers there.
@@ -138,6 +142,40 @@ static void stm32f7_mpu_config(void)
 	cortex_m3_mpu_enable(1);
 }
 
+#if defined(CONFIG_STM32F7_DCACHE_ON)
+/*
+ * Use 'dmamem' from cmdline passed to kernel to configure non-cacheable
+ * region appropriately ('dmamem' is in MB)
+ */
+void arch_preboot_os(void)
+{
+	char	buf[256], *s, *e;
+	char	*cmdline = getenv ("bootargs");
+	int	dmamem = 0;
+
+	if (!cmdline)
+		return;
+	s = strstr(cmdline, "dmamem=");
+	if (!s)
+		return;
+	s += strlen("dmamem=");
+	e = strchr(s, ' ');
+	strncpy(buf, s, e - s);
+	dmamem = simple_strtoul(buf, NULL, 10);
+	if (!dmamem)
+		return;
+
+	cortex_m3_mpu_enable(0);
+	cortex_m3_mpu_add_region(2,
+		(CONFIG_SYS_RAM_BASE + CONFIG_SYS_RAM_SIZE -
+		 (dmamem * 1024 * 1024)) | 1 << 4 | 2 << 0,
+		0 << 28 | 3 << 24 |
+		1 << 19 | 0 << 18 | 0 << 17 | 0 << 16 |
+		0 <<  8 | ((ffs(dmamem) + 18) <<  1) | 1 <<  0);
+	cortex_m3_mpu_enable(1);
+}
+#endif
+
 #if defined(CONFIG_STM32F7_ICACHE_ON) || defined(CONFIG_STM32F7_DCACHE_ON)
 /*
  * Enable Data and/or Instruction caches

include/configs/stm32f7-som.h

@@ -119,6 +119,12 @@
 #define CONFIG_STM32F7_DCACHE_ON
 /* #undef CONFIG_STM32F7_DCACHE_ON */
 
+#ifdef CONFIG_STM32F7_DCACHE_ON
+# define CONFIG_DMAMEM_SIZE		1	/* 1MB, must be a pwr of 2 */
+#else
+# define CONFIG_DMAMEM_SIZE		0
+#endif
+
 #define CONFIG_ARMCORTEXM3_SOC_INIT
 
 /*
@@ -332,7 +338,8 @@
 /* boot args and env */
 #define CONFIG_HOSTNAME			stm32f7-som
 #define CONFIG_BOOTARGS			"stm32_platform=stm32f7-som "	\
-					"console=ttyS0,115200 panic=10"
+					"console=ttyS0,115200 panic=10 "\
+					"dmamem=" MK_STR(CONFIG_DMAMEM_SIZE)
 
 #define LOADADDR			"0xC0007FC0"