Commit 64cd3322 authored by Vladimir Skvortsov's avatar Vladimir Skvortsov

RT106081:

Increase CPU frequency up to 200MHz on STM32F7-SOM.
parent 2d934a5e
/* /*
* (C) Copyright 2011 * (C) Copyright 2011, 2015
* *
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
* Vladimir Skvortsov, Emcraft Systems, vskvortsov@emcraft.com
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as
...@@ -139,9 +140,11 @@ ...@@ -139,9 +140,11 @@
# define STM32_FLASH_WS 4 # define STM32_FLASH_WS 4
#elif (STM32_SYS_CLK > 150000000) && (STM32_SYS_CLK <= 180000000) #elif (STM32_SYS_CLK > 150000000) && (STM32_SYS_CLK <= 180000000)
# define STM32_FLASH_WS 5 # define STM32_FLASH_WS 5
#elif (STM32_SYS_CLK > 180000000) && (STM32_SYS_CLK <= 250000000)
# define STM32_FLASH_WS 6
#else #else
# error "Incorrect System clock value configuration." # error "Incorrect System clock value configuration."
# define STM32_FLASH_WS 0 /* to avoid compile-time err */ # define STM32_FLASH_WS 0 /* to avoid compile-time err */
#endif #endif
/* /*
...@@ -152,6 +155,8 @@ ...@@ -152,6 +155,8 @@
#define STM32_RCC_CR_PLLON (1 << 24) /* PLL clock enable */ #define STM32_RCC_CR_PLLON (1 << 24) /* PLL clock enable */
#define STM32_RCC_CR_PLLRDY (1 << 25) /* PLL clock ready */ #define STM32_RCC_CR_PLLRDY (1 << 25) /* PLL clock ready */
#define STM32_RCC_APB1ENR_PWREN (1 << 28) /* Power interface clock enable */
#define STM32_RCC_CFGR_SW_BIT 0 /* System clock switch */ #define STM32_RCC_CFGR_SW_BIT 0 /* System clock switch */
#define STM32_RCC_CFGR_SW_MSK 0x3 #define STM32_RCC_CFGR_SW_MSK 0x3
#define STM32_RCC_CFGR_SWS_BIT 2 /* System clock switch status */ #define STM32_RCC_CFGR_SWS_BIT 2 /* System clock switch status */
...@@ -203,6 +208,15 @@ ...@@ -203,6 +208,15 @@
#define STM32_RCC_PLLCFGR_PLLQ_BIT 24 /* Div factor for USB,SDIO,.. */ #define STM32_RCC_PLLCFGR_PLLQ_BIT 24 /* Div factor for USB,SDIO,.. */
#define STM32_RCC_PLLCFGR_PLLQ_MSK 0xF #define STM32_RCC_PLLCFGR_PLLQ_MSK 0xF
/*
* Offsets and bitmasks of some PWR regs
*/
#define STM32_PWR_CR1_ODEN (1 << 16) /* Over-drive enable */
#define STM32_PWR_CR1_ODSWEN (1 << 17) /* Over-drive switching enabled */
#define STM32_PWR_CSR1_ODRDY (1 << 16) /* Over-drive mode ready */
#define STM32_PWR_CSR1_ODSWRDY (1 << 17) /* Over-drive mode switching ready */
/* /*
* Timeouts (in cycles) * Timeouts (in cycles)
*/ */
...@@ -213,6 +227,27 @@ ...@@ -213,6 +227,27 @@
*/ */
static u32 clock_val[CLOCK_END]; static u32 clock_val[CLOCK_END];
#if defined (CONFIG_SYS_STM32F7)
static int enable_over_drive(void)
{
uint32_t tickstart = 0;
STM32_RCC->apb1enr |= STM32_RCC_APB1ENR_PWREN;
/* Enable the Over-drive to extend the clock frequency to 200 Mhz */
STM32_PWR->cr1 |= STM32_PWR_CR1_ODEN;
/* Infinite wait! */
while (!(STM32_PWR->csr1 & STM32_PWR_CSR1_ODRDY)) {}
/* Enable the Over-drive switch */
STM32_PWR->cr1 |= STM32_PWR_CR1_ODSWEN;
/* Infinite wait! */
while (!(STM32_PWR->csr1 & STM32_PWR_CSR1_ODSWRDY));
return 0;
}
#endif
#if !defined(CONFIG_STM32_SYS_CLK_HSI) #if !defined(CONFIG_STM32_SYS_CLK_HSI)
/* /*
* Set-up clock configuration. * Set-up clock configuration.
...@@ -297,6 +332,10 @@ static void clock_setup(void) ...@@ -297,6 +332,10 @@ static void clock_setup(void)
val = STM32_RCC_CFGR_SWS_HSE; val = STM32_RCC_CFGR_SWS_HSE;
# endif /* CONFIG_STM32_SYS_CLK_PLL */ # endif /* CONFIG_STM32_SYS_CLK_PLL */
#if defined (CONFIG_SYS_STM32F7)
/* Enable over-drive in order to reach 200MHz */
enable_over_drive();
#endif
/* /*
* Configure Flash prefetch, Instruction cache, and wait * Configure Flash prefetch, Instruction cache, and wait
* latency. * latency.
......
/* /*
* (C) Copyright 2011 * (C) Copyright 2011, 2015
* *
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
* Vladimir Skvortsov, Emcraft Systems, vskvortsov@emcraft.com
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as
...@@ -93,6 +94,21 @@ enum clock { ...@@ -93,6 +94,21 @@ enum clock {
#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800) #define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
#define STM32_RCC ((volatile struct stm32_rcc_regs *) \ #define STM32_RCC ((volatile struct stm32_rcc_regs *) \
STM32_RCC_BASE) STM32_RCC_BASE)
/*
* PWR registers map
*/
struct stm32_pwr_regs {
u32 cr1; /* power control register 1 */
u32 csr1; /* power control/status register 2 */
u32 cr2; /* power control register 2 */
u32 csr2; /* power control/status register 2 */
};
#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
#define STM32_PWR ((volatile struct stm32_pwr_regs *) \
STM32_PWR_BASE)
/****************************************************************************** /******************************************************************************
* FIXME: get rid of this * FIXME: get rid of this
......
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
* Pavel Boldin, Emcraft Systems, paboldin@emcraft.com * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
* Vladimir Skvortsov, Emcraft Systems, vskvortsov@emcraft.com
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as
...@@ -91,9 +92,9 @@ ...@@ -91,9 +92,9 @@
#define CONFIG_STM32_PLL_SRC_HSE #define CONFIG_STM32_PLL_SRC_HSE
#define CONFIG_STM32_HSE_HZ 12000000 /* 12 MHz */ #define CONFIG_STM32_HSE_HZ 12000000 /* 12 MHz */
#define CONFIG_STM32_PLL_M 12 #define CONFIG_STM32_PLL_M 12
#define CONFIG_STM32_PLL_N 336 #define CONFIG_STM32_PLL_N 400
#define CONFIG_STM32_PLL_P 2 #define CONFIG_STM32_PLL_P 2
#define CONFIG_STM32_PLL_Q 7 #define CONFIG_STM32_PLL_Q 8
/* /*
* Number of clock ticks in 1 sec * Number of clock ticks in 1 sec
...@@ -162,15 +163,20 @@ ...@@ -162,15 +163,20 @@
#define CONFIG_SYS_FSMC_FLASH_BCR 0x00005059 #define CONFIG_SYS_FSMC_FLASH_BCR 0x00005059
/* /*
* Flash timinigs are almost same for write and read.
* See Spansion memory reference manual for S29GL128S10DHI010 * See Spansion memory reference manual for S29GL128S10DHI010
* tACC(MAX) = ADDSET(3-0) = 110 ns = 18.48 HCLK (on 168 MHz) * Read:
* tRC(MIN) = DATAST(15-8) = 110 ns = 18.48 HCLK (on 168 MHz) * ADDSET(3-0) = 25 ns = 5 HCLK (on 200 MHz)
* tNE switch = BUSTURN(19-16) = 10 ns = 2 HCLK * DATAST(15-8) = 110 ns = 22 HCLK (on 200 MHz)
* BUSTURN(19-16) = 10 ns = 2 HCLK
* ACCMODE(29-28) = 0x2 (mode C)
* Write:
* ADDSET(3-0) = 35 ns = 7 HCLK (on 200 MHz)
* DATAST(15-8) = 25 ns + 1HCLC = 6 HCLK (on 200 MHz)
* BUSTURN(19-16) = 10 ns = 2 HCLK
* ACCMODE(29-28) = 0x2 (mode C) * ACCMODE(29-28) = 0x2 (mode C)
*/ */
#define CONFIG_SYS_FSMC_FLASH_BTR 0x2002120f #define CONFIG_SYS_FSMC_FLASH_BTR 0x20021605
#define CONFIG_SYS_FSMC_FLASH_BWTR 0x2002110f #define CONFIG_SYS_FSMC_FLASH_BWTR 0x20020607
#define CONFIG_FSMC_NOR_PSRAM_CS1_ENABLE #define CONFIG_FSMC_NOR_PSRAM_CS1_ENABLE
#define CONFIG_SYS_FLASH_BANK1_BASE \ #define CONFIG_SYS_FLASH_BANK1_BASE \
...@@ -292,7 +298,7 @@ ...@@ -292,7 +298,7 @@
#if CONFIG_SYS_BOARD_REV == 0x1A #if CONFIG_SYS_BOARD_REV == 0x1A
# undef CONFIG_CMD_BUFCOPY # undef CONFIG_CMD_BUFCOPY
#else #else
# define CONFIG_CMD_BUFCOPY # define CONFIG_CMD_BUFCOPY
#endif #endif
......
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