RT73025. stm3220g-eval: external RAM support

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

board/stm/stm3220g-eval/board.c

@@ -26,8 +26,91 @@
 #include <common.h>
 #include <netdev.h>
 
+#include <asm/arch/stm32f2.h>
+#include <asm/arch/stm32f2_gpio.h>
+
+/*
+ * STM32F2 RCC FSMC specific definitions
+ */
+#define STM32F2_RCC_ENR_FSMC		(1 << 0)	/* FSMC module clock  */
+
+/*
+ * STM32F2 FSMC (Flexible static memory controller) definitions
+ */
+#define STM32F2_FSMC_BASE		0xA0000000
+
+/*
+ * BCR reg fields
+ */
+#define STM32F2_FSMC_BCR_MBKEN		(1 << 0)	/* Memory bank enble  */
+#define STM32F2_FSMC_BCR_MTYP_BIT	2		/* Memory type	      */
+#define STM32F2_FSMC_BCR_MTYP_SRAM_ROM	0x0		/* SRAM, ROM	      */
+#define STM32F2_FSMC_BCR_MWID_BIT	4		/* Databus width      */
+#define STM32F2_FSMC_BCR_MWID_16	0x1		/* 16 bits	      */
+#define STM32F2_FSMC_BCR_WREN		(1 << 12)	/* Write enable	      */
+
+/*
+ * BTR reg fields
+ */
+#define STM32F2_FSMC_BTR_DATAST_BIT	8		/* Data-phase time    */
+#define STM32F2_FSMC_BTR_BUSTURN_BIT	16		/* BusTurnaround time */
+
+/*
+ * BWTR regs fields
+ */
+#define STM32F2_FSMC_BWTR_ADDSET_BIT	0		/* Address setup time */
+#define STM32F2_FSMC_BWTR_ADDHLD_BIT	4		/* Address-hold time  */
+#define STM32F2_FSMC_BWTR_DATAST_BIT	8		/* Data-phase time    */
+#define STM32F2_FSMC_BWTR_BUSTURN_BIT	16		/* BusTurnaround time */
+#define STM32F2_FSMC_BWTR_CLKDIV_BIT	20		/* Clock divide ratio */
+#define STM32F2_FSMC_BWTR_DATLAN_BIT	24		/* Data latency	      */
+
+/*
+ * STM32F2 FSMC NOR/PSRAM controller register map
+ */
+struct stm32f2_fsmc_regs {
+	struct {
+		u32	bcr;		/* Chip-select control		      */
+		u32	btr;		/* Chip-select timing		      */
+	} cs[4];
+	u32	rsv0[57];
+	struct {
+		u32	wtr;		/* Write timing			      */
+		u32	rsv1;
+	} wt[4];
+};
+
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * External SRAM GPIOs:
+ *
+ * +-----------------+------------------+----------------+----------------+
+ * | PD0 <->FSMC_D2  | PE0 <->FSMC_NBL0 | PF0 <->FSMC_A0 | PG0<->FSMC_A10 |
+ * | PD1 <->FSMC_D3  | PE1 <->FSMC_NBL1 | PF1 <->FSMC_A1 | PG1<->FSMC_A11 |
+   | PD4 <->FSMC_NOE | PE3 <->FSMC_A19  | PF2 <->FSMC_A2 | PG2<->FSMC_A12 |
+   | PD5 <->FSMC_NWE | PE4 <->FSMC_A20  | PF3 <->FSMC_A3 | PG3<->FSMC_A13 |
+ * | PD8 <->FSMC_D13 | PE7 <->FSMC_D4   | PF5 <->FSMC_A5 | PG5<->FSMC_A15 |
+ * | PD9 <->FSMC_D14 | PE8 <->FSMC_D5   | PF12<->FSMC_A6 | PG9<->FSMC_NE2 |
+ * | PD10<->FSMC_D15 | PE9 <->FSMC_D6   | PF13<->FSMC_A7 +----------------+
+ * | PD11<->FSMC_A16 | PE10<->FSMC_D7   | PF14<->FSMC_A8 |
+ * | PD12<->FSMC_A17 | PE11<->FSMC_D8   | PF15<->FSMC_A9 |
+ * | PD13<->FSMC_A18 | PE12<->FSMC_D9   +----------------+
+ * | PD14<->FSMC_D0  | PE13<->FSMC_D10  |
+ * | PD15<->FSMC_D1  | PE14<->FSMC_D11  |
+ * +-----------------+ PE15<->FSMC_D12  |
+ *                   +------------------+
+ */
+static struct stm32f2_gpio_dsc fsmc_gpio[] = {
+	{3,  0}, {3,  1}, {3,  4}, {3,  5}, {3,  8}, {3,  9}, {3, 10}, {3, 11},
+	{3, 12}, {3, 13}, {3, 14}, {3, 15},
+	{4,  0}, {4,  1}, {4,  3}, {4,  4}, {4,  7}, {4,  8}, {4,  9}, {4, 10},
+	{4, 11}, {4, 12}, {4, 13}, {4, 14}, {4, 15},
+	{5,  0}, {5,  1}, {5,  2}, {5,  3}, {5,  4}, {5,  5}, {5, 12}, {5, 13},
+	{5, 14}, {5, 15},
+	{6,  0}, {6,  1}, {6,  2}, {6,  3}, {6,  4}, {6,  5}, {6,  9}
+};
+
 /*
  * Early hardware init.
  */
@@ -68,11 +151,68 @@ int misc_init_r(void)
  */
 int dram_init(void)
 {
+	int					rv = 0;
+
+#if (CONFIG_NR_DRAM_BANKS > 0)
+	volatile struct stm32f2_fsmc_regs	*fsmc_regs;
+	volatile struct stm32f2_rcc_regs	*rcc_regs;
+	int					i;
+
 	/*
-	 * TBD
+	 * Connect GPIOs to FSMC controller
 	 */
+	for (i = 0; i < sizeof(fsmc_gpio)/sizeof(fsmc_gpio[0]); i++) {
+		rv = stm32f2_gpio_config(&fsmc_gpio[i],
+					 STM32F2_GPIO_ROLE_FSMC);
+		if (rv != 0)
+			goto out;
+	}
 
-	return 0;
+	/*
+	 * Enable FSMC interface clock
+	 */
+	rcc_regs = (struct stm32f2_rcc_regs *)STM32F2_RCC_BASE;
+	rcc_regs->ahb3enr |= STM32F2_RCC_ENR_FSMC;
+
+	/*
+	 * Configure and enable Bank1 SRAM:
+	 * - 16 bit data bus;
+	 * - SRAM;
+	 * - Enabled;
+	 * - Maximum timings.
+	 */
+	fsmc_regs = (struct stm32f2_fsmc_regs *)STM32F2_FSMC_BASE;
+
+	/*
+	 * Fake BCR read; if don't do this, then BCR remains configured
+	 * with defaults.
+	 */
+	rv = fsmc_regs->cs[1].bcr;
+	fsmc_regs->cs[1].bcr = STM32F2_FSMC_BCR_WREN |
+			       (STM32F2_FSMC_BCR_MWID_16 <<
+				STM32F2_FSMC_BCR_MWID_BIT) |
+			       (STM32F2_FSMC_BCR_MTYP_SRAM_ROM <<
+				STM32F2_FSMC_BCR_MTYP_BIT) |
+			       STM32F2_FSMC_BCR_MBKEN;
+	fsmc_regs->cs[1].btr = (1 << STM32F2_FSMC_BTR_BUSTURN_BIT) |
+			       (4 << STM32F2_FSMC_BTR_DATAST_BIT);
+	fsmc_regs->wt[1].wtr = (0x0F << STM32F2_FSMC_BWTR_DATLAN_BIT) |
+			       (0x0F << STM32F2_FSMC_BWTR_CLKDIV_BIT) |
+			       (0x0F << STM32F2_FSMC_BWTR_BUSTURN_BIT) |
+			       (0xFF << STM32F2_FSMC_BWTR_DATAST_BIT) |
+			       (0x0F << STM32F2_FSMC_BWTR_ADDHLD_BIT) |
+			       (0x0F << STM32F2_FSMC_BWTR_ADDSET_BIT);
+
+	/*
+	 * Fill in global info with description of SRAM configuration
+	 */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
+	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
+
+	rv = 0;
+out:
+#endif /* CONFIG_NR_DRAM_BANKS */
+	return rv;
 }
 
 #ifdef CONFIG_STM32F2_ETH

include/configs/stm3220g-eval.h

@@ -111,10 +111,11 @@
 #define CONFIG_SYS_MALLOC_LEN		CONFIG_MEM_MALLOC_LEN
 
 /*
- * Configuration of the external memory
+ * Configuration of the external memory:
+ * 2MB SRAM connected to CS2 of Bank1 (NOR/PSRAM)
  */
 #define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_SYS_RAM_BASE		0x60000000
+#define CONFIG_SYS_RAM_BASE		0x64000000
 #define CONFIG_SYS_RAM_SIZE		(2 * 1024 * 1024)
 
 /*
@@ -231,8 +232,7 @@
  * Short-cuts to some useful commands (macros)
  */
 #define CONFIG_EXTRA_ENV_SETTINGS				\
-	/* FIXME: load to external RAM */			\
-	"loadaddr=0x20008000\0"					\
+	"loadaddr=0x64000000\0"					\
 	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off\0"				\
 	"ethaddr=C0:B1:3C:88:88:88\0"				\
 	"ipaddr=172.17.4.206\0"					\