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Sami Nurmenniemi
u-boot-stm32
Commits
6c99130e
Commit
6c99130e
authored
Oct 11, 2011
by
Yuri Tikhonov
Browse files
RT72064. stm32: minor identation fixes
Signed-off-by:
Yuri Tikhonov
<
yur@emcraft.com
>
parent
fd070806
Changes
2
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Inline
Side-by-side
cpu/arm_cortexm3/stm32/clock.c
View file @
6c99130e
...
...
@@ -268,8 +268,7 @@ static void clock_setup(void)
val
|=
CONFIG_STM32_PLL_M
<<
STM32_RCC_PLLCFGR_PLLM_BIT
;
val
|=
CONFIG_STM32_PLL_N
<<
STM32_RCC_PLLCFGR_PLLN_BIT
;
val
|=
((
CONFIG_STM32_PLL_P
>>
1
)
-
1
)
<<
STM32_RCC_PLLCFGR_PLLP_BIT
;
val
|=
((
CONFIG_STM32_PLL_P
>>
1
)
-
1
)
<<
STM32_RCC_PLLCFGR_PLLP_BIT
;
val
|=
CONFIG_STM32_PLL_Q
<<
STM32_RCC_PLLCFGR_PLLQ_BIT
;
STM32_RCC
->
pllcfgr
=
val
;
...
...
@@ -306,11 +305,10 @@ static void clock_setup(void)
/*
* Change system clock source, and wait (infinite!) till it done
*/
STM32_RCC
->
cfgr
&=
~
(
STM32_RCC_CFGR_SW_MSK
<<
STM32_RCC_CFGR_SW_BIT
);
STM32_RCC
->
cfgr
&=
~
(
STM32_RCC_CFGR_SW_MSK
<<
STM32_RCC_CFGR_SW_BIT
);
STM32_RCC
->
cfgr
|=
val
<<
STM32_RCC_CFGR_SW_BIT
;
while
((
STM32_RCC
->
cfgr
&
(
STM32_RCC_CFGR_SWS_MSK
<<
STM32_RCC_CFGR_SWS_BIT
))
!=
STM32_RCC_CFGR_SWS_BIT
))
!=
(
val
<<
STM32_RCC_CFGR_SWS_BIT
));
out:
return
;
...
...
drivers/net/stm32_eth.c
View file @
6c99130e
...
...
@@ -731,8 +731,7 @@ static void stm_mac_bd_init(struct stm_eth_dev *mac)
*/
for
(
i
=
0
;
i
<
PKTBUFSRX
;
i
++
)
{
mac
->
rx_bd
[
i
].
stat
=
STM32_DMA_RBD_DMA_OWN
;
mac
->
rx_bd
[
i
].
ctrl
=
STM32_DMA_RBD_RCH
|
PKTSIZE_ALIGN
;
mac
->
rx_bd
[
i
].
ctrl
=
STM32_DMA_RBD_RCH
|
PKTSIZE_ALIGN
;
mac
->
rx_bd
[
i
].
buf
=
&
mac
->
rx_buf
[
i
][
0
];
mac
->
rx_bd
[
i
].
next
=
&
mac
->
rx_bd
[(
i
+
1
)
%
PKTBUFSRX
];
}
...
...
@@ -762,11 +761,11 @@ static void stm_mac_address_set(struct stm_eth_dev *mac)
netdev
->
enetaddr
[
4
],
netdev
->
enetaddr
[
5
]);
STM32_MAC
->
maca0hr
=
(
netdev
->
enetaddr
[
5
]
<<
8
)
|
(
netdev
->
enetaddr
[
4
]
<<
0
);
(
netdev
->
enetaddr
[
4
]
<<
0
);
STM32_MAC
->
maca0lr
=
(
netdev
->
enetaddr
[
3
]
<<
24
)
|
(
netdev
->
enetaddr
[
2
]
<<
16
)
|
(
netdev
->
enetaddr
[
1
]
<<
8
)
|
(
netdev
->
enetaddr
[
0
]
<<
0
);
(
netdev
->
enetaddr
[
2
]
<<
16
)
|
(
netdev
->
enetaddr
[
1
]
<<
8
)
|
(
netdev
->
enetaddr
[
0
]
<<
0
);
}
/*
...
...
@@ -861,8 +860,8 @@ static int stm_mac_hw_init(struct stm_eth_dev *mac)
* Enable Ethernet clocks
*/
STM32_RCC
->
ahb1enr
|=
STM32_RCC_ENR_ETHMACEN
|
STM32_RCC_ENR_ETHMACTXEN
|
STM32_RCC_ENR_ETHMACRXEN
;
STM32_RCC_ENR_ETHMACTXEN
|
STM32_RCC_ENR_ETHMACRXEN
;
/*
* Reset all MAC subsystem internal regs and logic
...
...
@@ -890,12 +889,11 @@ static int stm_mac_hw_init(struct stm_eth_dev *mac)
* - enable use of separate PBL for Rx and Tx.
*/
STM32_MAC
->
dmabmr
=
(
32
<<
STM32_MAC_DMABMR_PBL_BIT
)
|
(
STM32_MAC_DMABMR_RTPR_2_1
<<
STM32_MAC_DMABMR_RTPR_BIT
)
|
STM32_MAC_DMABMR_FB
|
(
32
<<
STM32_MAC_DMABMR_RDP_BIT
)
|
STM32_MAC_DMABMR_USP
|
STM32_MAC_DMABMR_AAB
;
(
32
<<
STM32_MAC_DMABMR_RDP_BIT
)
|
(
STM32_MAC_DMABMR_RTPR_2_1
<<
STM32_MAC_DMABMR_RTPR_BIT
)
|
STM32_MAC_DMABMR_FB
|
STM32_MAC_DMABMR_USP
|
STM32_MAC_DMABMR_AAB
;
/*
* Configure Ethernet CSR Clock Range
...
...
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