Commit 791d3ebe authored by Alexander Potashev's avatar Alexander Potashev
Browse files

RT77744. lpc4350-eval: Ethernet support

 * Write a custom Ethernet driver for LPC18xx/LPC43xx. We know the
Ethernet module is compatible with STM32F, but we do not want to spend
time right now to merge these drivers.
 * Use Ethernet MII mode.
 * Store Ethernet DMA buffers and buffer descriptors in a free region of
internal SRAM.
parent 6a2c27cd
......@@ -259,6 +259,48 @@ static const struct lpc18xx_pin_config hitex_lpc4350_iomux[] = {
{{CONFIG_LPC18XX_UART_RX_IO_GROUP, CONFIG_LPC18XX_UART_RX_IO_PIN},
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 1, 0)},
#ifdef CONFIG_LPC18XX_ETH
/*
* Pin configuration for Ethernet (MII + MDIO)
*/
/* PC.1 = ENET_MDC */
{{0xC, 1}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P1.17 = ENET_MDIO (high-drive pin) */
{{0x1, 17}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P1.18 = ENET_TXD0 */
{{0x1, 18}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P1.20 = ENET_TXD1 */
{{0x1, 20}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P9.4 = ENET_TXD2 */
{{0x9, 4}, LPC18XX_IOMUX_CONFIG(5, 0, 1, 0, 1, 1)},
/* P9.5 = ENET_TXD3 */
{{0x9, 5}, LPC18XX_IOMUX_CONFIG(5, 0, 1, 0, 1, 1)},
/* P0.1 = ENET_TX_EN */
{{0x0, 1}, LPC18XX_IOMUX_CONFIG(6, 0, 1, 0, 1, 1)},
/* P1.15 = ENET_RXD0 */
{{0x1, 15}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P0.0 = ENET_RXD1 */
{{0x0, 0}, LPC18XX_IOMUX_CONFIG(2, 0, 1, 0, 1, 1)},
/* P9.3 = ENET_RXD2 */
{{0x9, 3}, LPC18XX_IOMUX_CONFIG(5, 0, 1, 0, 1, 1)},
/* P9.2 = ENET_RXD3 */
{{0x9, 2}, LPC18XX_IOMUX_CONFIG(5, 0, 1, 0, 1, 1)},
/* P9.0 = ENET_CRS */
{{0x9, 0}, LPC18XX_IOMUX_CONFIG(5, 0, 1, 0, 1, 1)},
/* P9.1 = ENET_RX_ER */
{{0x9, 1}, LPC18XX_IOMUX_CONFIG(5, 0, 1, 0, 1, 1)},
/* PC.0 = ENET_RX_CLK */
{{0xC, 0}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* PC.5 = ENET_TX_ER */
{{0xC, 5}, LPC18XX_IOMUX_CONFIG(3, 0, 1, 0, 1, 1)},
/* P9.6 = ENET_COL */
{{0x9, 6}, LPC18XX_IOMUX_CONFIG(5, 0, 1, 0, 1, 1)},
/* P1.19 = ENET_TX_CLK */
{{0x1, 19}, LPC18XX_IOMUX_CONFIG(0, 0, 1, 0, 1, 1)},
/* P1.16 = ENET_RXDV */
{{0x1, 16}, LPC18XX_IOMUX_CONFIG(7, 0, 1, 0, 1, 1)},
#endif /* CONFIG_LPC18XX_ETH */
#if defined(CONFIG_NR_DRAM_BANKS) || defined(CONFIG_SYS_FLASH_CS)
/*
* EMC pins used for both the SDRAM and the NOR flash memory chips
......@@ -527,3 +569,13 @@ int dram_init(void)
return 0;
}
#ifdef CONFIG_LPC18XX_ETH
/*
* Register ethernet driver
*/
int board_eth_init(bd_t *bis)
{
return lpc18xx_eth_driver_init(bis);
}
#endif
......@@ -22,6 +22,7 @@
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/lpc18xx_creg.h>
#include "clock.h"
/*
......@@ -109,6 +110,10 @@ struct lpc18xx_cgu_regs {
/* CLK_SEL: Clock source selection */
#define LPC18XX_CGU_CLKSEL_BITS 24
#define LPC18XX_CGU_CLKSEL_MSK (0x1f << LPC18XX_CGU_CLKSEL_BITS)
/* ENET_RX_CLK */
#define LPC18XX_CGU_CLKSEL_ENET_RX (0x02 << LPC18XX_CGU_CLKSEL_BITS)
/* ENET_TX_CLK */
#define LPC18XX_CGU_CLKSEL_ENET_TX (0x03 << LPC18XX_CGU_CLKSEL_BITS)
/* Crystal oscillator */
#define LPC18XX_CGU_CLKSEL_XTAL (0x06 << LPC18XX_CGU_CLKSEL_BITS)
/* PLL1 */
......@@ -144,6 +149,42 @@ struct lpc18xx_cgu_regs {
/* PLL1 lock indicator */
#define LPC18XX_CGU_PLL1STAT_LOCK (1 << 0)
/*
* RGU (Reset Generation Unit) register map
*/
struct lpc18xx_rgu_regs {
u32 rsv0[64];
u32 ctrl0; /* Reset control register 0 */
u32 ctrl1; /* Reset control register 1 */
u32 rsv1[2];
u32 status0; /* Reset status register 0 */
u32 status1; /* Reset status register 1 */
u32 status2; /* Reset status register 2 */
u32 status3; /* Reset status register 3 */
u32 rsv2[12];
u32 active_status0; /* Reset active status register 0 */
u32 active_status1; /* Reset active status register 1 */
u32 rsv3[170];
u32 ext_stat[64]; /* Reset external status registers */
};
/*
* RGU registers base
*/
#define LPC18XX_RGU_BASE 0x40053000
#define LPC18XX_RGU ((volatile struct lpc18xx_rgu_regs *) \
LPC18XX_RGU_BASE)
/*
* RESET_CTRL0 register
*/
/* ETHERNET_RST */
#define LPC18XX_RGU_CTRL0_ETHERNET (1 << 22)
/*
* Clock values
*/
......@@ -301,6 +342,55 @@ static void clock_setup(void)
LPC18XX_CGU_AUTOBLOCK_MSK;
}
/*
* Set-up the Ethernet clock and reset the Ethernet MAC
*/
void eth_clock_setup(void)
{
int timeout;
int rv;
/*
* This clock configuration is valid only for MII
*/
LPC18XX_CGU->phy_rx_clk =
LPC18XX_CGU_CLKSEL_ENET_RX | LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->phy_tx_clk =
LPC18XX_CGU_CLKSEL_ENET_TX | LPC18XX_CGU_AUTOBLOCK_MSK;
/*
* Choose the MII Ethernet mode
*/
LPC18XX_CREG->creg6 =
(LPC18XX_CREG->creg6 & ~LPC18XX_CREG_CREG6_ETHMODE_MSK) |
LPC18XX_CREG_CREG6_ETHMODE_MII;
/*
* Reset the Ethernet module of the MCU
*/
LPC18XX_RGU->ctrl0 = LPC18XX_RGU_CTRL0_ETHERNET;
/*
* Wait for the Ethernet module to exit the reset state
*/
timeout = 10;
rv = -ETIMEDOUT;
while (timeout-- > 0) {
if (!(LPC18XX_RGU->active_status0 &
LPC18XX_RGU_CTRL0_ETHERNET)) {
udelay(1000);
} else {
timeout = 0;
rv = 0;
}
}
if (rv < 0) {
printf("%s: Reset of the Ethernet module timed out.\n",
__func__);
}
}
/*
* Initialize the reference clocks.
*/
......@@ -311,6 +401,11 @@ void clock_init(void)
*/
clock_setup();
/*
* Set-up Ethernet clocks
*/
eth_clock_setup();
/*
* Set SysTick timer rate to the CPU core clock
*/
......
......@@ -78,6 +78,7 @@ COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
COBJS-$(CONFIG_CORE10100) += core10100.o
COBJS-$(CONFIG_STM32_ETH) += stm32_eth.o
COBJS-$(CONFIG_LPC178X_ETH) += lpc178x_eth.o
COBJS-$(CONFIG_LPC18XX_ETH) += lpc18xx_eth.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
......
This diff is collapsed.
......@@ -131,6 +131,10 @@
#define CONFIG_SYS_RAM_CS 0 /* 0 .. 3 */
#define CONFIG_SYS_RAM_BASE 0x28000000
#define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024)
/*
* Buffers for Ethernet DMA (cannot be in the internal System RAM)
*/
#define CONFIG_MEM_ETH_DMA_BUF_BASE 0x10080000 /* Region of SRAM */
/*
* Use the CPU_CLOCK/2 for EMC
*/
......@@ -184,6 +188,24 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Ethernet configuration
*/
#define CONFIG_NET_MULTI
#define CONFIG_LPC18XX_ETH
#define CONFIG_LPC18XX_ETH_DIV_SEL 4 /* 150-250 MHz */
/*
* Ethernet RX buffers are malloced from the internal SRAM (more precisely,
* from CONFIG_SYS_MALLOC_LEN part of it). Each RX buffer has size of 1536B.
* So, keep this in mind when changing the value of the following config,
* which determines the number of ethernet RX buffers (number of frames which
* may be received without processing until overflow happens).
*/
#define CONFIG_SYS_RX_ETH_BUFFER 3
#define CONFIG_SYS_TX_ETH_BUFFER 3
/*
* Console I/O buffer size
*/
......@@ -230,7 +252,7 @@
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#define CONFIG_CMD_NET /* Obligatory for the Ethernet driver to build */
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
......
......@@ -88,6 +88,7 @@ int dm9000_initialize(bd_t *bis);
int core_eth_init(bd_t *bis);
int stm32_eth_init(bd_t *bis);
int lpc178x_eth_driver_init(bd_t *bis);
int lpc18xx_eth_driver_init(bd_t *bis);
/* Boards with PCI network controllers can call this from their board_eth_init()
* function to initialize whatever's on board.
......
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