From 7de399c179a54d6cf2e7cbfc7191109a2f41935c Mon Sep 17 00:00:00 2001 From: Alexander Potashev Date: Tue, 24 Jan 2012 21:45:09 +0400 Subject: [PATCH] RT75957. twr-k70f120m: NAND Flash support; environment in flash This patch consists of the following: 1. NAND Flash Controller (NFC) pin configuration. 2. NFC clock configuration (enable the clock, initialize the clock rate.) 3. Changes to the `fsl_nfc` NFC driver: * Code cleanup (there were compilation warnings, e.g. unused data and functions.) * `#include ` should not be used on ARM. * Disable the GPIO configuration code on ARM. * Use `__raw_writel/__raw_readl` instead of `out_be32/in_be32`. The registers of the NAND Flash Controller always use the same endianness as the MCU core. * Make the code in fsl_nfc_get_id() and fsl_nfc_get_status() endianness-independent (they were accessing the data from 32-bit register as an array of u8, this approach is endianness-dependent.) 4. NAND support in the U-Boot configuration file. 5. Support for environment in the NAND flash in the U-Boot configuration file. 6. Increase the size of the `RAM` memory region to fit the statically allocated data for the NAND driver and the U-Boot framework for NAND. --- board/freescale/twr-k70f120m/board.c | 55 ++++++++ cpu/arm_cortexm3/kinetis/clock.c | 26 +++- cpu/arm_cortexm3/kinetis/soc.c | 7 + drivers/mtd/nand/fsl_nfc.c | 142 ++++---------------- include/asm-arm/arch-kinetis/kinetis.h | 2 + include/asm-arm/arch-kinetis/kinetis_gpio.h | 5 + include/configs/twr-k70f120m.h | 28 ++-- include/mtd/fsl_nfc.h | 61 ++------- 8 files changed, 151 insertions(+), 175 deletions(-) diff --git a/board/freescale/twr-k70f120m/board.c b/board/freescale/twr-k70f120m/board.c index 830b194..7f0b283 100644 --- a/board/freescale/twr-k70f120m/board.c +++ b/board/freescale/twr-k70f120m/board.c @@ -374,6 +374,61 @@ static const struct kinetis_gpio_pin_config twr_k70f120m_gpio[] = { /* B.1 = RMII0_MDC */ {{KINETIS_GPIO_PORT_B, 1}, KINETIS_GPIO_CONFIG_MUX(4)}, #endif /* CONFIG_MCFFEC */ + +#ifdef CONFIG_CMD_NAND + /* C.17 = NFC_CE0 (our flash is on chip select 0) */ + {{KINETIS_GPIO_PORT_C, 17}, KINETIS_GPIO_CONFIG_DSE(6)}, + + /* + * NAND Flash control pins + */ + /* C.16 = NFC_RB */ + {{KINETIS_GPIO_PORT_C, 16}, KINETIS_GPIO_CONFIG_DSE(6)}, + /* D.8 = NFC_CLE */ + {{KINETIS_GPIO_PORT_D, 8}, KINETIS_GPIO_CONFIG_DSE(6)}, + /* D.9 = NFC_ALE */ + {{KINETIS_GPIO_PORT_D, 9}, KINETIS_GPIO_CONFIG_DSE(6)}, + /* D.10 = NFC_RE */ + {{KINETIS_GPIO_PORT_D, 10}, KINETIS_GPIO_CONFIG_DSE(6)}, + /* C.11 = NFC_WE */ + {{KINETIS_GPIO_PORT_C, 11}, KINETIS_GPIO_CONFIG_DSE(5)}, + + /* + * NAND Flash data pins (the flash is 16-bit) + */ + /* D.5 = NFC_D0 */ + {{KINETIS_GPIO_PORT_D, 5}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* D.4 = NFC_D1 */ + {{KINETIS_GPIO_PORT_D, 4}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.10 = NFC_D2 */ + {{KINETIS_GPIO_PORT_C, 10}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.9 = NFC_D3 */ + {{KINETIS_GPIO_PORT_C, 9}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.8 = NFC_D4 */ + {{KINETIS_GPIO_PORT_C, 8}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.7 = NFC_D5 */ + {{KINETIS_GPIO_PORT_C, 7}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.6 = NFC_D6 */ + {{KINETIS_GPIO_PORT_C, 6}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.5 = NFC_D7 */ + {{KINETIS_GPIO_PORT_C, 5}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.4 = NFC_D8 */ + {{KINETIS_GPIO_PORT_C, 4}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.2 = NFC_D9 */ + {{KINETIS_GPIO_PORT_C, 2}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.1 = NFC_D10 */ + {{KINETIS_GPIO_PORT_C, 1}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* C.0 = NFC_D11 */ + {{KINETIS_GPIO_PORT_C, 0}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* B.23 = NFC_D12 */ + {{KINETIS_GPIO_PORT_B, 23}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* B.22 = NFC_D13 */ + {{KINETIS_GPIO_PORT_B, 22}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* B.21 = NFC_D14 */ + {{KINETIS_GPIO_PORT_B, 21}, KINETIS_GPIO_CONFIG_DSE(5)}, + /* B.20 = NFC_D15 */ + {{KINETIS_GPIO_PORT_B, 20}, KINETIS_GPIO_CONFIG_DSE(5)}, +#endif /* CONFIG_CMD_NAND */ }; /* diff --git a/cpu/arm_cortexm3/kinetis/clock.c b/cpu/arm_cortexm3/kinetis/clock.c index dce75a5..74f94b5 100644 --- a/cpu/arm_cortexm3/kinetis/clock.c +++ b/cpu/arm_cortexm3/kinetis/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2011 + * (C) Copyright 2011, 2012 * * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com * @@ -336,6 +336,21 @@ #define KINETIS_SIM_CLKDIV1_OUTDIV3_BITS 20 /* Clock 4 output divider value (for the flash clock) */ #define KINETIS_SIM_CLKDIV1_OUTDIV4_BITS 16 +/* + * System Clock Divider Register 4 + */ +/* NFC clock divider divisor */ +#define KINETIS_SIM_CLKDIV4_NFCDIV_BITS 27 +#define KINETIS_SIM_CLKDIV4_NFCDIV_BITWIDTH 5 +#define KINETIS_SIM_CLKDIV4_NFCDIV_MSK \ + (((1 << KINETIS_SIM_CLKDIV4_NFCDIV_BITWIDTH) - 1) << \ + KINETIS_SIM_CLKDIV4_NFCDIV_BITS) +/* NFC clock divider fraction */ +#define KINETIS_SIM_CLKDIV4_NFCFRAC_BITS 24 +#define KINETIS_SIM_CLKDIV4_NFCFRAC_BITWIDTH 3 +#define KINETIS_SIM_CLKDIV4_NFCFRAC_MSK \ + (((1 << KINETIS_SIM_CLKDIV4_NFCFRAC_BITWIDTH) - 1) << \ + KINETIS_SIM_CLKDIV4_NFCFRAC_BITS) /* * Multipurpose Clock Generator (MCG) register map @@ -563,6 +578,15 @@ static void clock_setup(void) ((KINETIS_FLASH_CLK_DIV - 1) << KINETIS_SIM_CLKDIV1_OUTDIV4_BITS); + /* + * Configure clock divider for the NAND Flash Controller + */ + KINETIS_SIM->clkdiv4 = + (KINETIS_SIM->clkdiv4 & ~(KINETIS_SIM_CLKDIV4_NFCDIV_MSK | + KINETIS_SIM_CLKDIV4_NFCFRAC_MSK)) | + ((KINETIS_NFCCLK_DIV - 1) << KINETIS_SIM_CLKDIV4_NFCDIV_BITS) | + ((KINETIS_NFCCLK_FRAC - 1) << KINETIS_SIM_CLKDIV4_NFCFRAC_BITS); + /* * TBD: Configure clock dividers for USB and I2S here * via KINETIS_SIM->clkdiv2 diff --git a/cpu/arm_cortexm3/kinetis/soc.c b/cpu/arm_cortexm3/kinetis/soc.c index c7da4a9..16a9537 100644 --- a/cpu/arm_cortexm3/kinetis/soc.c +++ b/cpu/arm_cortexm3/kinetis/soc.c @@ -52,6 +52,13 @@ void cortex_m3_soc_init(void) kinetis_periph_enable(KINETIS_CG_ENET, 1); #endif /* CONFIG_MCFFEC */ +#ifdef CONFIG_CMD_NAND + /* + * Enable the clock on the NAND Flash Controller module of the MCU + */ + kinetis_periph_enable(KINETIS_CG_NFC, 1); +#endif /* CONFIG_CMD_NAND */ + /* * Disable the MPU to let the Ethernet module access the SRAM */ diff --git a/drivers/mtd/nand/fsl_nfc.c b/drivers/mtd/nand/fsl_nfc.c index 0b26e37..2b2bec2 100644 --- a/drivers/mtd/nand/fsl_nfc.c +++ b/drivers/mtd/nand/fsl_nfc.c @@ -10,6 +10,10 @@ * * Based on original driver mpc5121_nfc.c. * + * (C) Copyright 2012 + * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com + * Add support for Freescale Kinetis, used by TWR-K70F120M + * * This is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -30,7 +34,10 @@ #include #include #include + +#ifdef CONFIG_M68K #include +#endif #define DRV_NAME "fsl_nfc" #define DRV_VERSION "0.5" @@ -42,7 +49,9 @@ #define ECC_STATUS_MASK 0x80 #define ECC_ERR_COUNT 0x3F +#ifndef MIN #define MIN(x, y) ((x < y) ? x : y) +#endif #ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC static int hardware_ecc; @@ -58,7 +67,6 @@ struct fsl_nfc_prv { struct clk *clk; uint column; int spareonly; - u8 *testbuf; }; int fsl_nfc_chip; @@ -89,16 +97,6 @@ static struct nand_bbt_descr bbt_mirror_descr = { .pattern = mirror_pattern, }; -static struct nand_ecclayout nand_hw_eccoob_512 = { - .eccbytes = 8, - .eccpos = { - 8, 9, 10, 11, 12, 13, 14, 15, - }, - .oobfree = { - {0, 5} /* byte 5 is factory bad block marker */ - }, -}; - static struct nand_ecclayout fsl_nfc_ecc45 = { .eccbytes = 45, .eccpos = {19, 20, 21, 22, 23, @@ -112,68 +110,12 @@ static struct nand_ecclayout fsl_nfc_ecc45 = { .length = 11} } }; -static struct nand_ecclayout fsl_nfc_ecc15 = { - .eccbytes = 15, - .eccpos = {49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63}, - .oobfree = { - {.offset = 8, - .length = 41} } -}; - -static struct nand_ecclayout fsl_nfc_ecc23 = { - .eccbytes = 23, - .eccpos = {41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63}, - .oobfree = { - {.offset = 8, - .length = 33} } -}; - - -static struct nand_ecclayout nand_hw_eccoob_2k = { - .eccbytes = 32, - .eccpos = { - /* 8 bytes of ecc for each 512 bytes of data */ - 8, 9, 10, 11, 12, 13, 14, 15, - 24, 25, 26, 27, 28, 29, 30, 31, - 40, 41, 42, 43, 44, 45, 46, 47, - 56, 57, 58, 59, 60, 61, 62, 63, - }, - .oobfree = { - {2, 5}, /* bytes 0 and 1 are factory bad block markers */ - {16, 7}, - {32, 7}, - {48, 7}, - }, -}; - - -/* ecc struct for nand 5125 */ -static struct nand_ecclayout nand5125_hw_eccoob_2k = { - .eccbytes = 60, - .eccpos = { - /* 60 bytes of ecc for one page bytes of data */ - 4, 5, - 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, - 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, - 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, - 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63, - }, - .oobfree = { - {2, 2}, /* bytes 0 and 1 are factory bad block markers */ - }, -}; - static inline u32 nfc_read(struct mtd_info *mtd, uint reg) { struct nand_chip *chip = mtd->priv; struct fsl_nfc_prv *prv = chip->priv; - return in_be32(prv->regs + reg); + return __raw_readl(prv->regs + reg); } /* Write NFC register */ @@ -182,7 +124,7 @@ static inline void nfc_write(struct mtd_info *mtd, uint reg, u32 val) struct nand_chip *chip = mtd->priv; struct fsl_nfc_prv *prv = chip->priv; - out_be32(prv->regs + reg, val); + __raw_writel(val, prv->regs + reg); } /* Set bits in NFC register */ @@ -203,9 +145,8 @@ nfc_set_field(struct mtd_info *mtd, u32 reg, u32 mask, u32 shift, u32 val) struct nand_chip *chip = mtd->priv; struct fsl_nfc_prv *prv = chip->priv; - out_be32(prv->regs + reg, - (in_be32(prv->regs + reg) & (~mask)) - | val << shift); + __raw_writel((__raw_readl(prv->regs + reg) & (~mask)) | val << shift, + prv->regs + reg); } static inline int @@ -214,7 +155,7 @@ nfc_get_field(struct mtd_info *mtd, u32 reg, u32 field_mask) struct nand_chip *chip = mtd->priv; struct fsl_nfc_prv *prv = chip->priv; - return in_be32(prv->regs + reg) & field_mask; + return __raw_readl(prv->regs + reg) & field_mask; } static inline u8 nfc_check_status(struct mtd_info *mtd) @@ -234,8 +175,6 @@ static void fsl_nfc_clear(struct mtd_info *mtd) /* Wait for operation complete */ static void fsl_nfc_done(struct mtd_info *mtd) { - struct nand_chip *chip = mtd->priv; - struct fsl_nfc_prv *prv = chip->priv; uint start = 0; nfc_set_field(mtd, NFC_FLASH_CMD2, START_MASK, @@ -246,6 +185,7 @@ static void fsl_nfc_done(struct mtd_info *mtd) while (!nfc_get_field(mtd, NFC_IRQ_STATUS, CMD_DONE_IRQ_MASK)) { if (get_timer(start) > NFC_TIMEOUT) { printf("Timeout while waiting for BUSY.\n"); + break; } } fsl_nfc_clear(mtd); @@ -253,24 +193,18 @@ static void fsl_nfc_done(struct mtd_info *mtd) static u8 fsl_nfc_get_id(struct mtd_info *mtd, int col) { - u32 flash_id1 = 0; - u8 *pid; - - flash_id1 = nfc_read(mtd, NFC_FLASH_STATUS1); - pid = (u8 *)&flash_id1; - - return *(pid + col); + /* + * Get the (col+1)th byte from the Flash Status Register 1 + */ + return (u8)(nfc_read(mtd, NFC_FLASH_STATUS1) >> ((3 - col) * 8)); } static inline u8 fsl_nfc_get_status(struct mtd_info *mtd) { - u32 flash_status = 0; - u8 *pstatus; - - flash_status = nfc_read(mtd, NFC_FLASH_STATUS2); - pstatus = (u8 *)&flash_status; - - return *(pstatus + 3); + /* + * Get the byte returned by the read status command + */ + return (u8)nfc_read(mtd, NFC_FLASH_STATUS2); } /* Invoke command cycle */ @@ -343,6 +277,7 @@ fsl_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) static void m54418twr_select_chip(struct mtd_info *mtd, int chip) { +#ifdef CONFIG_M68K volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; if (chip < 0) { @@ -366,6 +301,7 @@ m54418twr_select_chip(struct mtd_info *mtd, int chip) GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0; gpio->par_cs &= (GPIO_PAR_BE_BE3_MASK & GPIO_PAR_BE_BE2_MASK); gpio->par_cs = GPIO_PAR_CS_CS1_NFC_CE; +#endif /* CONFIG_M68K */ } void board_nand_select_device(struct nand_chip *nand, int chip) @@ -626,24 +562,6 @@ fsl_nfc_read_word(struct mtd_info *mtd) return tmp; } -static void fsl_nfc_check_ecc_status(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd->priv; - struct fsl_nfc_prv *prv = chip->priv; - u8 ecc_status, ecc_count; - - ecc_status = *(u8 *)(prv->regs + ECC_SRAM_ADDR * 8 + 7); - ecc_count = ecc_status & ECC_ERR_COUNT; - if (ecc_status & ECC_STATUS_MASK) { - /*mtd->ecc_stats.failed++;*/ - printf("ECC failed to correct all errors!\n"); - } else if (ecc_count) { - /*mtd->ecc_stats.corrected += ecc_count;*/ - printf("ECC corrected %d errors\n", ecc_count); - } - -} - static void copy_from_to_spare(struct mtd_info *mtd, void *pbuf, int len, int wr) { @@ -706,10 +624,9 @@ static int fsl_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, } static int fsl_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf) + uint8_t *buf, int page) { struct fsl_nfc_prv *prv = chip->priv; - /*fsl_nfc_check_ecc_status(mtd);*/ memcpy((void *)buf, prv->regs + NFC_MAIN_AREA(0), mtd->writesize); @@ -733,14 +650,9 @@ static void fsl_nfc_enable_hwecc(struct mtd_info *mtd, int mode) int board_nand_init(struct nand_chip *chip) { struct fsl_nfc_prv *prv; - struct resource *res; struct mtd_info *mtd; uint chips_no = 0; - int retval = 0; - u8 *testbuf; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile ccm_t *ccm = (gpio_t *) MMAP_CCM; if (chip->IO_ADDR_R == NULL) { return -1; @@ -757,7 +669,6 @@ int board_nand_init(struct nand_chip *chip) chip->priv = prv; prv->regs = (void __iomem *)chip->IO_ADDR_R; - prv->testbuf = testbuf; mtd->name = "NAND"; mtd->writesize = 2048; @@ -841,4 +752,3 @@ int board_nand_init(struct nand_chip *chip) #endif return 0; } - diff --git a/include/asm-arm/arch-kinetis/kinetis.h b/include/asm-arm/arch-kinetis/kinetis.h index 63903ec..db3c928 100644 --- a/include/asm-arm/arch-kinetis/kinetis.h +++ b/include/asm-arm/arch-kinetis/kinetis.h @@ -90,6 +90,8 @@ typedef u32 kinetis_clock_gate_t; #define KINETIS_CG_ENET KINETIS_MKCG(1, 0) /* SIM_SCGC2[0] */ /* DDR */ #define KINETIS_CG_DDR KINETIS_MKCG(2, 14) /* SIM_SCGC3[14] */ +/* NAND Flash Controller */ +#define KINETIS_CG_NFC KINETIS_MKCG(2, 8) /* SIM_SCGC3[8] */ /* * Limits for the `kinetis_periph_enable()` function: diff --git a/include/asm-arm/arch-kinetis/kinetis_gpio.h b/include/asm-arm/arch-kinetis/kinetis_gpio.h index d50bb39..6c13419 100644 --- a/include/asm-arm/arch-kinetis/kinetis_gpio.h +++ b/include/asm-arm/arch-kinetis/kinetis_gpio.h @@ -30,6 +30,8 @@ /* Pull Enable (pull-down by default) */ #define KINETIS_GPIO_CONFIG_PE_BIT 1 #define KINETIS_GPIO_CONFIG_PE_MSK (1 << KINETIS_GPIO_CONFIG_PE_BIT) +/* Drive Strength Enable (high drive strength) */ +#define KINETIS_GPIO_CONFIG_DSE_MSK (1 << 6) /* * These macros should be used to compute the value for the second argument of @@ -42,6 +44,9 @@ /* Also enable the pull-down register */ #define KINETIS_GPIO_CONFIG_PULLDOWN(mux) \ (KINETIS_GPIO_CONFIG_MUX(mux) | KINETIS_GPIO_CONFIG_PE_MSK) +/* Also enable high drive strength */ +#define KINETIS_GPIO_CONFIG_DSE(mux) \ + (KINETIS_GPIO_CONFIG_MUX(mux) | KINETIS_GPIO_CONFIG_DSE_MSK) /* * TBD: similar macros with more options */ diff --git a/include/configs/twr-k70f120m.h b/include/configs/twr-k70f120m.h index c85a253..3b088d7 100644 --- a/include/configs/twr-k70f120m.h +++ b/include/configs/twr-k70f120m.h @@ -98,6 +98,10 @@ #define KINETIS_FLEXBUS_CLK_DIV 3 /* Flash clock divider: 120/5 = 24 MHz */ #define KINETIS_FLASH_CLK_DIV 5 +/* NFC clock divider: PLL0/5 = 120/5 = 24 MHz */ +#define KINETIS_NFCCLK_DIV 5 +/* NFC clock fraction: do no multiply */ +#define KINETIS_NFCCLK_FRAC 1 /* PLL input divider: 50/5 = 10 MHz */ #define KINETIS_PLL_PRDIV 5 /* PLL multiplier: 10*24/2 = 120 MHz */ @@ -147,8 +151,8 @@ * SRAM_U: 0x20000000 - 0x2000FFFF (64 kB) */ #define CONFIG_MEM_RAM_BASE 0x1FFF0000 -#define CONFIG_MEM_RAM_LEN (22 * 1024) -#define CONFIG_MEM_RAM_BUF_LEN (84 * 1024) +#define CONFIG_MEM_RAM_LEN (32 * 1024) +#define CONFIG_MEM_RAM_BUF_LEN (74 * 1024) #define CONFIG_MEM_MALLOC_LEN (18 * 1024) #define CONFIG_MEM_STACK_LEN (4 * 1024) /* @@ -171,16 +175,23 @@ /* * Configuration of the external Flash memory */ +/* No NOR flash present */ #define CONFIG_SYS_NO_FLASH +/* NAND Flash configuration */ +#define CONFIG_NAND_FSL_NFC +#define CONFIG_SYS_NAND_BASE 0x400A8000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ /* - * Store env in memory only + * Store environment in the NAND Flash */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE (4 * 1024) -#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BANK1_BASE -#define CONFIG_INFERNO 1 -#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* * Serial console configuration @@ -286,6 +297,7 @@ #undef CONFIG_CMD_NFS #undef CONFIG_CMD_SOURCE #undef CONFIG_CMD_XIMG +#define CONFIG_CMD_NAND /* * To save memory disable long help diff --git a/include/mtd/fsl_nfc.h b/include/mtd/fsl_nfc.h index 1efa04d..f33d433 100644 --- a/include/mtd/fsl_nfc.h +++ b/include/mtd/fsl_nfc.h @@ -16,45 +16,6 @@ #define MPC5125_NFC_H -/* NFC PAD Define */ -#define PAD_NFC_IO PAD_FUNC0 -#define PAD_NFC_ALE PAD_FUNC0 -#define PAD_NFC_CLE PAD_FUNC0 -#define PAD_NFC_WE PAD_FUNC0 -#define PAD_NFC_RE PAD_FUNC0 -#define PAD_NFC_CE0 PAD_FUNC0 -#define PAD_NFC_CE1 PAD_FUNC1 -#define PAD_NFC_CE2 PAD_FUNC2 -#define PAD_NFC_CE3 PAD_FUNC2 -#define PAD_NFC_RB0 PAD_FUNC0 -#define PAD_NFC_RB1 PAD_FUNC2 -#define PAD_NFC_RB2 PAD_FUNC2 -#define PAD_NFC_RB3 PAD_FUNC2 - -/* NFC Control PAD Define */ -#define BALL_NFC_CE0 IOCTL_NFC_CE0_B -#define BALL_NFC_CE1 IOCTL_SDHC1_CLK -#define BALL_NFC_CE2 IOCTL_PSC1_4 -#define BALL_NFC_CE3 IOCTL_J1850_TX -#define BALL_NFC_RB0 IOCTL_NFC_RB -#define BALL_NFC_RB1 IOCTL_FEC1_TXD_0 -#define BALL_NFC_RB2 IOCTL_PSC1_3 -#define BALL_NFC_RB3 IOCTL_J1850_RX -#define BALL_NFC_ALE IOCTL_EMB_AD19 -#define BALL_NFC_CLE IOCTL_EMB_AD18 -#define BALL_NFC_WE IOCTL_EMB_AD16 -#define BALL_NFC_RE IOCTL_EMB_AD17 - -/* NFC IO Pad Define */ -#define BALL_NFC_IO0 IOCTL_EMB_AD00 -#define BALL_NFC_IO1 IOCTL_EMB_AD01 -#define BALL_NFC_IO2 IOCTL_EMB_AD02 -#define BALL_NFC_IO3 IOCTL_EMB_AD03 -#define BALL_NFC_IO4 IOCTL_EMB_AD04 -#define BALL_NFC_IO5 IOCTL_EMB_AD05 -#define BALL_NFC_IO6 IOCTL_EMB_AD06 -#define BALL_NFC_IO7 IOCTL_EMB_AD07 - /* Addresses for NFC MAIN RAM BUFFER areas */ #define NFC_MAIN_AREA(n) ((n) * 0x1000) @@ -63,8 +24,8 @@ #define NFC_SPARE_LEN 0x10 #define NFC_SPARE_AREA(n) (0x800 + ((n) * NFC_SPARE_LEN)) -#define PAGE_2K 0x0800 -#define PAGE_64 0x0040 +#define PAGE_2K 0x0800 +#define PAGE_64 0x0040 /* MPC5125 NFC registers */ /* Typical Flash Commands */ @@ -104,7 +65,7 @@ /***************** Module-Relative Register Offsets *************************/ #define NFC_SRAM_BUFFER 0x0000 -#define NFC_FLASH_CMD1 0x3F00 +#define NFC_FLASH_CMD1 0x3F00 #define NFC_FLASH_CMD2 0x3F04 #define NFC_COL_ADDR 0x3F08 #define NFC_ROW_ADDR 0x3F0c @@ -121,8 +82,8 @@ #define NFC_IRQ_STATUS 0x3F38 /***************** Module-Relative Register Reset Value *********************/ -#define NFC_SRAM_BUFFER_RSTVAL 0x00000000 -#define NFC_FLASH_CMD1_RSTVAL 0x30FF0000 +#define NFC_SRAM_BUFFER_RSTVAL 0x00000000 +#define NFC_FLASH_CMD1_RSTVAL 0x30FF0000 #define NFC_FLASH_CMD2_RSTVAL 0x007EE000 #define NFC_COL_ADDR_RSTVAL 0x00000000 #define NFC_ROW_ADDR_RSTVAL 0x11000000 @@ -143,16 +104,16 @@ /* NFC_FLASH_CMD1 Field */ #define CMD1_MASK 0xFFFF0000 #define CMD1_SHIFT 0 -#define CMD_BYTE2_MASK 0xFF000000 -#define CMD_BYTE2_SHIFT 24 -#define CMD_BYTE3_MASK 0x00FF0000 -#define CMD_BYTE3_SHIFT 16 +#define CMD_BYTE2_MASK 0xFF000000 +#define CMD_BYTE2_SHIFT 24 +#define CMD_BYTE3_MASK 0x00FF0000 +#define CMD_BYTE3_SHIFT 16 /* NFC_FLASH_CM2 Field */ #define CMD2_MASK 0xFFFFFF07 #define CMD2_SHIFT 0 -#define CMD_BYTE1_MASK 0xFF000000 -#define CMD_BYTE1_SHIFT 24 +#define CMD_BYTE1_MASK 0xFF000000 +#define CMD_BYTE1_SHIFT 24 #define CMD_CODE_MASK 0x00FFFF00 #define CMD_CODE_SHIFT 8 #define BUFNO_MASK 0x00000006 -- GitLab