Commit 7de399c1 authored by Alexander Potashev's avatar Alexander Potashev

RT75957. twr-k70f120m: NAND Flash support; environment in flash

This patch consists of the following:
1. NAND Flash Controller (NFC) pin configuration.
2. NFC clock configuration (enable the clock, initialize the clock rate.)
3. Changes to the `fsl_nfc` NFC driver:
     * Code cleanup (there were compilation warnings, e.g. unused data
         and functions.)
     * `#include <asm/immap.h>` should not be used on ARM.
     * Disable the GPIO configuration code on ARM.
     * Use `__raw_writel/__raw_readl` instead of `out_be32/in_be32`.
         The registers of the NAND Flash Controller always use the
         same endianness as the MCU core.
     * Make the code in fsl_nfc_get_id() and fsl_nfc_get_status()
         endianness-independent (they were accessing the data from
         32-bit register as an array of u8, this approach is
         endianness-dependent.)
4. NAND support in the U-Boot configuration file.
5. Support for environment in the NAND flash in the U-Boot configuration
     file.
6. Increase the size of the `RAM` memory region to fit the statically
allocated data for the NAND driver and the U-Boot framework for NAND.
parent be6ee378
...@@ -374,6 +374,61 @@ static const struct kinetis_gpio_pin_config twr_k70f120m_gpio[] = { ...@@ -374,6 +374,61 @@ static const struct kinetis_gpio_pin_config twr_k70f120m_gpio[] = {
/* B.1 = RMII0_MDC */ /* B.1 = RMII0_MDC */
{{KINETIS_GPIO_PORT_B, 1}, KINETIS_GPIO_CONFIG_MUX(4)}, {{KINETIS_GPIO_PORT_B, 1}, KINETIS_GPIO_CONFIG_MUX(4)},
#endif /* CONFIG_MCFFEC */ #endif /* CONFIG_MCFFEC */
#ifdef CONFIG_CMD_NAND
/* C.17 = NFC_CE0 (our flash is on chip select 0) */
{{KINETIS_GPIO_PORT_C, 17}, KINETIS_GPIO_CONFIG_DSE(6)},
/*
* NAND Flash control pins
*/
/* C.16 = NFC_RB */
{{KINETIS_GPIO_PORT_C, 16}, KINETIS_GPIO_CONFIG_DSE(6)},
/* D.8 = NFC_CLE */
{{KINETIS_GPIO_PORT_D, 8}, KINETIS_GPIO_CONFIG_DSE(6)},
/* D.9 = NFC_ALE */
{{KINETIS_GPIO_PORT_D, 9}, KINETIS_GPIO_CONFIG_DSE(6)},
/* D.10 = NFC_RE */
{{KINETIS_GPIO_PORT_D, 10}, KINETIS_GPIO_CONFIG_DSE(6)},
/* C.11 = NFC_WE */
{{KINETIS_GPIO_PORT_C, 11}, KINETIS_GPIO_CONFIG_DSE(5)},
/*
* NAND Flash data pins (the flash is 16-bit)
*/
/* D.5 = NFC_D0 */
{{KINETIS_GPIO_PORT_D, 5}, KINETIS_GPIO_CONFIG_DSE(5)},
/* D.4 = NFC_D1 */
{{KINETIS_GPIO_PORT_D, 4}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.10 = NFC_D2 */
{{KINETIS_GPIO_PORT_C, 10}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.9 = NFC_D3 */
{{KINETIS_GPIO_PORT_C, 9}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.8 = NFC_D4 */
{{KINETIS_GPIO_PORT_C, 8}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.7 = NFC_D5 */
{{KINETIS_GPIO_PORT_C, 7}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.6 = NFC_D6 */
{{KINETIS_GPIO_PORT_C, 6}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.5 = NFC_D7 */
{{KINETIS_GPIO_PORT_C, 5}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.4 = NFC_D8 */
{{KINETIS_GPIO_PORT_C, 4}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.2 = NFC_D9 */
{{KINETIS_GPIO_PORT_C, 2}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.1 = NFC_D10 */
{{KINETIS_GPIO_PORT_C, 1}, KINETIS_GPIO_CONFIG_DSE(5)},
/* C.0 = NFC_D11 */
{{KINETIS_GPIO_PORT_C, 0}, KINETIS_GPIO_CONFIG_DSE(5)},
/* B.23 = NFC_D12 */
{{KINETIS_GPIO_PORT_B, 23}, KINETIS_GPIO_CONFIG_DSE(5)},
/* B.22 = NFC_D13 */
{{KINETIS_GPIO_PORT_B, 22}, KINETIS_GPIO_CONFIG_DSE(5)},
/* B.21 = NFC_D14 */
{{KINETIS_GPIO_PORT_B, 21}, KINETIS_GPIO_CONFIG_DSE(5)},
/* B.20 = NFC_D15 */
{{KINETIS_GPIO_PORT_B, 20}, KINETIS_GPIO_CONFIG_DSE(5)},
#endif /* CONFIG_CMD_NAND */
}; };
/* /*
......
/* /*
* (C) Copyright 2011 * (C) Copyright 2011, 2012
* *
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
* *
...@@ -336,6 +336,21 @@ ...@@ -336,6 +336,21 @@
#define KINETIS_SIM_CLKDIV1_OUTDIV3_BITS 20 #define KINETIS_SIM_CLKDIV1_OUTDIV3_BITS 20
/* Clock 4 output divider value (for the flash clock) */ /* Clock 4 output divider value (for the flash clock) */
#define KINETIS_SIM_CLKDIV1_OUTDIV4_BITS 16 #define KINETIS_SIM_CLKDIV1_OUTDIV4_BITS 16
/*
* System Clock Divider Register 4
*/
/* NFC clock divider divisor */
#define KINETIS_SIM_CLKDIV4_NFCDIV_BITS 27
#define KINETIS_SIM_CLKDIV4_NFCDIV_BITWIDTH 5
#define KINETIS_SIM_CLKDIV4_NFCDIV_MSK \
(((1 << KINETIS_SIM_CLKDIV4_NFCDIV_BITWIDTH) - 1) << \
KINETIS_SIM_CLKDIV4_NFCDIV_BITS)
/* NFC clock divider fraction */
#define KINETIS_SIM_CLKDIV4_NFCFRAC_BITS 24
#define KINETIS_SIM_CLKDIV4_NFCFRAC_BITWIDTH 3
#define KINETIS_SIM_CLKDIV4_NFCFRAC_MSK \
(((1 << KINETIS_SIM_CLKDIV4_NFCFRAC_BITWIDTH) - 1) << \
KINETIS_SIM_CLKDIV4_NFCFRAC_BITS)
/* /*
* Multipurpose Clock Generator (MCG) register map * Multipurpose Clock Generator (MCG) register map
...@@ -563,6 +578,15 @@ static void clock_setup(void) ...@@ -563,6 +578,15 @@ static void clock_setup(void)
((KINETIS_FLASH_CLK_DIV - 1) << ((KINETIS_FLASH_CLK_DIV - 1) <<
KINETIS_SIM_CLKDIV1_OUTDIV4_BITS); KINETIS_SIM_CLKDIV1_OUTDIV4_BITS);
/*
* Configure clock divider for the NAND Flash Controller
*/
KINETIS_SIM->clkdiv4 =
(KINETIS_SIM->clkdiv4 & ~(KINETIS_SIM_CLKDIV4_NFCDIV_MSK |
KINETIS_SIM_CLKDIV4_NFCFRAC_MSK)) |
((KINETIS_NFCCLK_DIV - 1) << KINETIS_SIM_CLKDIV4_NFCDIV_BITS) |
((KINETIS_NFCCLK_FRAC - 1) << KINETIS_SIM_CLKDIV4_NFCFRAC_BITS);
/* /*
* TBD: Configure clock dividers for USB and I2S here * TBD: Configure clock dividers for USB and I2S here
* via KINETIS_SIM->clkdiv2 * via KINETIS_SIM->clkdiv2
......
...@@ -52,6 +52,13 @@ void cortex_m3_soc_init(void) ...@@ -52,6 +52,13 @@ void cortex_m3_soc_init(void)
kinetis_periph_enable(KINETIS_CG_ENET, 1); kinetis_periph_enable(KINETIS_CG_ENET, 1);
#endif /* CONFIG_MCFFEC */ #endif /* CONFIG_MCFFEC */
#ifdef CONFIG_CMD_NAND
/*
* Enable the clock on the NAND Flash Controller module of the MCU
*/
kinetis_periph_enable(KINETIS_CG_NFC, 1);
#endif /* CONFIG_CMD_NAND */
/* /*
* Disable the MPU to let the Ethernet module access the SRAM * Disable the MPU to let the Ethernet module access the SRAM
*/ */
......
...@@ -10,6 +10,10 @@ ...@@ -10,6 +10,10 @@
* *
* Based on original driver mpc5121_nfc.c. * Based on original driver mpc5121_nfc.c.
* *
* (C) Copyright 2012
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
* Add support for Freescale Kinetis, used by TWR-K70F120M
*
* This is free software; you can redistribute it and/or modify it * This is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by * under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; either version 2 of the License, or
...@@ -30,7 +34,10 @@ ...@@ -30,7 +34,10 @@
#include <asm/errno.h> #include <asm/errno.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/processor.h> #include <asm/processor.h>
#ifdef CONFIG_M68K
#include <asm/immap.h> #include <asm/immap.h>
#endif
#define DRV_NAME "fsl_nfc" #define DRV_NAME "fsl_nfc"
#define DRV_VERSION "0.5" #define DRV_VERSION "0.5"
...@@ -42,7 +49,9 @@ ...@@ -42,7 +49,9 @@
#define ECC_STATUS_MASK 0x80 #define ECC_STATUS_MASK 0x80
#define ECC_ERR_COUNT 0x3F #define ECC_ERR_COUNT 0x3F
#ifndef MIN
#define MIN(x, y) ((x < y) ? x : y) #define MIN(x, y) ((x < y) ? x : y)
#endif
#ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC #ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC
static int hardware_ecc; static int hardware_ecc;
...@@ -58,7 +67,6 @@ struct fsl_nfc_prv { ...@@ -58,7 +67,6 @@ struct fsl_nfc_prv {
struct clk *clk; struct clk *clk;
uint column; uint column;
int spareonly; int spareonly;
u8 *testbuf;
}; };
int fsl_nfc_chip; int fsl_nfc_chip;
...@@ -89,16 +97,6 @@ static struct nand_bbt_descr bbt_mirror_descr = { ...@@ -89,16 +97,6 @@ static struct nand_bbt_descr bbt_mirror_descr = {
.pattern = mirror_pattern, .pattern = mirror_pattern,
}; };
static struct nand_ecclayout nand_hw_eccoob_512 = {
.eccbytes = 8,
.eccpos = {
8, 9, 10, 11, 12, 13, 14, 15,
},
.oobfree = {
{0, 5} /* byte 5 is factory bad block marker */
},
};
static struct nand_ecclayout fsl_nfc_ecc45 = { static struct nand_ecclayout fsl_nfc_ecc45 = {
.eccbytes = 45, .eccbytes = 45,
.eccpos = {19, 20, 21, 22, 23, .eccpos = {19, 20, 21, 22, 23,
...@@ -112,68 +110,12 @@ static struct nand_ecclayout fsl_nfc_ecc45 = { ...@@ -112,68 +110,12 @@ static struct nand_ecclayout fsl_nfc_ecc45 = {
.length = 11} } .length = 11} }
}; };
static struct nand_ecclayout fsl_nfc_ecc15 = {
.eccbytes = 15,
.eccpos = {49, 50, 51, 52, 53, 54, 55,
56, 57, 58, 59, 60, 61, 62, 63},
.oobfree = {
{.offset = 8,
.length = 41} }
};
static struct nand_ecclayout fsl_nfc_ecc23 = {
.eccbytes = 23,
.eccpos = {41, 42, 43, 44, 45, 46, 47,
48, 49, 50, 51, 52, 53, 54, 55,
56, 57, 58, 59, 60, 61, 62, 63},
.oobfree = {
{.offset = 8,
.length = 33} }
};
static struct nand_ecclayout nand_hw_eccoob_2k = {
.eccbytes = 32,
.eccpos = {
/* 8 bytes of ecc for each 512 bytes of data */
8, 9, 10, 11, 12, 13, 14, 15,
24, 25, 26, 27, 28, 29, 30, 31,
40, 41, 42, 43, 44, 45, 46, 47,
56, 57, 58, 59, 60, 61, 62, 63,
},
.oobfree = {
{2, 5}, /* bytes 0 and 1 are factory bad block markers */
{16, 7},
{32, 7},
{48, 7},
},
};
/* ecc struct for nand 5125 */
static struct nand_ecclayout nand5125_hw_eccoob_2k = {
.eccbytes = 60,
.eccpos = {
/* 60 bytes of ecc for one page bytes of data */
4, 5,
6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31, 32, 33, 34, 35,
36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
56, 57, 58, 59, 60, 61, 62, 63,
},
.oobfree = {
{2, 2}, /* bytes 0 and 1 are factory bad block markers */
},
};
static inline u32 nfc_read(struct mtd_info *mtd, uint reg) static inline u32 nfc_read(struct mtd_info *mtd, uint reg)
{ {
struct nand_chip *chip = mtd->priv; struct nand_chip *chip = mtd->priv;
struct fsl_nfc_prv *prv = chip->priv; struct fsl_nfc_prv *prv = chip->priv;
return in_be32(prv->regs + reg); return __raw_readl(prv->regs + reg);
} }
/* Write NFC register */ /* Write NFC register */
...@@ -182,7 +124,7 @@ static inline void nfc_write(struct mtd_info *mtd, uint reg, u32 val) ...@@ -182,7 +124,7 @@ static inline void nfc_write(struct mtd_info *mtd, uint reg, u32 val)
struct nand_chip *chip = mtd->priv; struct nand_chip *chip = mtd->priv;
struct fsl_nfc_prv *prv = chip->priv; struct fsl_nfc_prv *prv = chip->priv;
out_be32(prv->regs + reg, val); __raw_writel(val, prv->regs + reg);
} }
/* Set bits in NFC register */ /* Set bits in NFC register */
...@@ -203,9 +145,8 @@ nfc_set_field(struct mtd_info *mtd, u32 reg, u32 mask, u32 shift, u32 val) ...@@ -203,9 +145,8 @@ nfc_set_field(struct mtd_info *mtd, u32 reg, u32 mask, u32 shift, u32 val)
struct nand_chip *chip = mtd->priv; struct nand_chip *chip = mtd->priv;
struct fsl_nfc_prv *prv = chip->priv; struct fsl_nfc_prv *prv = chip->priv;
out_be32(prv->regs + reg, __raw_writel((__raw_readl(prv->regs + reg) & (~mask)) | val << shift,
(in_be32(prv->regs + reg) & (~mask)) prv->regs + reg);
| val << shift);
} }
static inline int static inline int
...@@ -214,7 +155,7 @@ nfc_get_field(struct mtd_info *mtd, u32 reg, u32 field_mask) ...@@ -214,7 +155,7 @@ nfc_get_field(struct mtd_info *mtd, u32 reg, u32 field_mask)
struct nand_chip *chip = mtd->priv; struct nand_chip *chip = mtd->priv;
struct fsl_nfc_prv *prv = chip->priv; struct fsl_nfc_prv *prv = chip->priv;
return in_be32(prv->regs + reg) & field_mask; return __raw_readl(prv->regs + reg) & field_mask;
} }
static inline u8 nfc_check_status(struct mtd_info *mtd) static inline u8 nfc_check_status(struct mtd_info *mtd)
...@@ -234,8 +175,6 @@ static void fsl_nfc_clear(struct mtd_info *mtd) ...@@ -234,8 +175,6 @@ static void fsl_nfc_clear(struct mtd_info *mtd)
/* Wait for operation complete */ /* Wait for operation complete */
static void fsl_nfc_done(struct mtd_info *mtd) static void fsl_nfc_done(struct mtd_info *mtd)
{ {
struct nand_chip *chip = mtd->priv;
struct fsl_nfc_prv *prv = chip->priv;
uint start = 0; uint start = 0;
nfc_set_field(mtd, NFC_FLASH_CMD2, START_MASK, nfc_set_field(mtd, NFC_FLASH_CMD2, START_MASK,
...@@ -246,6 +185,7 @@ static void fsl_nfc_done(struct mtd_info *mtd) ...@@ -246,6 +185,7 @@ static void fsl_nfc_done(struct mtd_info *mtd)
while (!nfc_get_field(mtd, NFC_IRQ_STATUS, CMD_DONE_IRQ_MASK)) { while (!nfc_get_field(mtd, NFC_IRQ_STATUS, CMD_DONE_IRQ_MASK)) {
if (get_timer(start) > NFC_TIMEOUT) { if (get_timer(start) > NFC_TIMEOUT) {
printf("Timeout while waiting for BUSY.\n"); printf("Timeout while waiting for BUSY.\n");
break;
} }
} }
fsl_nfc_clear(mtd); fsl_nfc_clear(mtd);
...@@ -253,24 +193,18 @@ static void fsl_nfc_done(struct mtd_info *mtd) ...@@ -253,24 +193,18 @@ static void fsl_nfc_done(struct mtd_info *mtd)
static u8 fsl_nfc_get_id(struct mtd_info *mtd, int col) static u8 fsl_nfc_get_id(struct mtd_info *mtd, int col)
{ {
u32 flash_id1 = 0; /*
u8 *pid; * Get the (col+1)th byte from the Flash Status Register 1
*/
flash_id1 = nfc_read(mtd, NFC_FLASH_STATUS1); return (u8)(nfc_read(mtd, NFC_FLASH_STATUS1) >> ((3 - col) * 8));
pid = (u8 *)&flash_id1;
return *(pid + col);
} }
static inline u8 fsl_nfc_get_status(struct mtd_info *mtd) static inline u8 fsl_nfc_get_status(struct mtd_info *mtd)
{ {
u32 flash_status = 0; /*
u8 *pstatus; * Get the byte returned by the read status command
*/
flash_status = nfc_read(mtd, NFC_FLASH_STATUS2); return (u8)nfc_read(mtd, NFC_FLASH_STATUS2);
pstatus = (u8 *)&flash_status;
return *(pstatus + 3);
} }
/* Invoke command cycle */ /* Invoke command cycle */
...@@ -343,6 +277,7 @@ fsl_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) ...@@ -343,6 +277,7 @@ fsl_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
static void static void
m54418twr_select_chip(struct mtd_info *mtd, int chip) m54418twr_select_chip(struct mtd_info *mtd, int chip)
{ {
#ifdef CONFIG_M68K
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if (chip < 0) { if (chip < 0) {
...@@ -366,6 +301,7 @@ m54418twr_select_chip(struct mtd_info *mtd, int chip) ...@@ -366,6 +301,7 @@ m54418twr_select_chip(struct mtd_info *mtd, int chip)
GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0; GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0;
gpio->par_cs &= (GPIO_PAR_BE_BE3_MASK & GPIO_PAR_BE_BE2_MASK); gpio->par_cs &= (GPIO_PAR_BE_BE3_MASK & GPIO_PAR_BE_BE2_MASK);
gpio->par_cs = GPIO_PAR_CS_CS1_NFC_CE; gpio->par_cs = GPIO_PAR_CS_CS1_NFC_CE;
#endif /* CONFIG_M68K */
} }
void board_nand_select_device(struct nand_chip *nand, int chip) void board_nand_select_device(struct nand_chip *nand, int chip)
...@@ -626,24 +562,6 @@ fsl_nfc_read_word(struct mtd_info *mtd) ...@@ -626,24 +562,6 @@ fsl_nfc_read_word(struct mtd_info *mtd)
return tmp; return tmp;
} }
static void fsl_nfc_check_ecc_status(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
struct fsl_nfc_prv *prv = chip->priv;
u8 ecc_status, ecc_count;
ecc_status = *(u8 *)(prv->regs + ECC_SRAM_ADDR * 8 + 7);
ecc_count = ecc_status & ECC_ERR_COUNT;
if (ecc_status & ECC_STATUS_MASK) {
/*mtd->ecc_stats.failed++;*/
printf("ECC failed to correct all errors!\n");
} else if (ecc_count) {
/*mtd->ecc_stats.corrected += ecc_count;*/
printf("ECC corrected %d errors\n", ecc_count);
}
}
static void static void
copy_from_to_spare(struct mtd_info *mtd, void *pbuf, int len, int wr) copy_from_to_spare(struct mtd_info *mtd, void *pbuf, int len, int wr)
{ {
...@@ -706,10 +624,9 @@ static int fsl_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, ...@@ -706,10 +624,9 @@ static int fsl_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
} }
static int fsl_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, static int fsl_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
uint8_t *buf) uint8_t *buf, int page)
{ {
struct fsl_nfc_prv *prv = chip->priv; struct fsl_nfc_prv *prv = chip->priv;
/*fsl_nfc_check_ecc_status(mtd);*/
memcpy((void *)buf, prv->regs + NFC_MAIN_AREA(0), memcpy((void *)buf, prv->regs + NFC_MAIN_AREA(0),
mtd->writesize); mtd->writesize);
...@@ -733,14 +650,9 @@ static void fsl_nfc_enable_hwecc(struct mtd_info *mtd, int mode) ...@@ -733,14 +650,9 @@ static void fsl_nfc_enable_hwecc(struct mtd_info *mtd, int mode)
int board_nand_init(struct nand_chip *chip) int board_nand_init(struct nand_chip *chip)
{ {
struct fsl_nfc_prv *prv; struct fsl_nfc_prv *prv;
struct resource *res;
struct mtd_info *mtd; struct mtd_info *mtd;
uint chips_no = 0; uint chips_no = 0;
int retval = 0;
u8 *testbuf;
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile ccm_t *ccm = (gpio_t *) MMAP_CCM;
if (chip->IO_ADDR_R == NULL) { if (chip->IO_ADDR_R == NULL) {
return -1; return -1;
...@@ -757,7 +669,6 @@ int board_nand_init(struct nand_chip *chip) ...@@ -757,7 +669,6 @@ int board_nand_init(struct nand_chip *chip)
chip->priv = prv; chip->priv = prv;
prv->regs = (void __iomem *)chip->IO_ADDR_R; prv->regs = (void __iomem *)chip->IO_ADDR_R;
prv->testbuf = testbuf;
mtd->name = "NAND"; mtd->name = "NAND";
mtd->writesize = 2048; mtd->writesize = 2048;
...@@ -841,4 +752,3 @@ int board_nand_init(struct nand_chip *chip) ...@@ -841,4 +752,3 @@ int board_nand_init(struct nand_chip *chip)
#endif #endif
return 0; return 0;
} }
...@@ -90,6 +90,8 @@ typedef u32 kinetis_clock_gate_t; ...@@ -90,6 +90,8 @@ typedef u32 kinetis_clock_gate_t;
#define KINETIS_CG_ENET KINETIS_MKCG(1, 0) /* SIM_SCGC2[0] */ #define KINETIS_CG_ENET KINETIS_MKCG(1, 0) /* SIM_SCGC2[0] */
/* DDR */ /* DDR */
#define KINETIS_CG_DDR KINETIS_MKCG(2, 14) /* SIM_SCGC3[14] */ #define KINETIS_CG_DDR KINETIS_MKCG(2, 14) /* SIM_SCGC3[14] */
/* NAND Flash Controller */
#define KINETIS_CG_NFC KINETIS_MKCG(2, 8) /* SIM_SCGC3[8] */
/* /*
* Limits for the `kinetis_periph_enable()` function: * Limits for the `kinetis_periph_enable()` function:
......
...@@ -30,6 +30,8 @@ ...@@ -30,6 +30,8 @@
/* Pull Enable (pull-down by default) */ /* Pull Enable (pull-down by default) */
#define KINETIS_GPIO_CONFIG_PE_BIT 1 #define KINETIS_GPIO_CONFIG_PE_BIT 1
#define KINETIS_GPIO_CONFIG_PE_MSK (1 << KINETIS_GPIO_CONFIG_PE_BIT) #define KINETIS_GPIO_CONFIG_PE_MSK (1 << KINETIS_GPIO_CONFIG_PE_BIT)
/* Drive Strength Enable (high drive strength) */
#define KINETIS_GPIO_CONFIG_DSE_MSK (1 << 6)
/* /*
* These macros should be used to compute the value for the second argument of * These macros should be used to compute the value for the second argument of
...@@ -42,6 +44,9 @@ ...@@ -42,6 +44,9 @@
/* Also enable the pull-down register */ /* Also enable the pull-down register */
#define KINETIS_GPIO_CONFIG_PULLDOWN(mux) \ #define KINETIS_GPIO_CONFIG_PULLDOWN(mux) \
(KINETIS_GPIO_CONFIG_MUX(mux) | KINETIS_GPIO_CONFIG_PE_MSK) (KINETIS_GPIO_CONFIG_MUX(mux) | KINETIS_GPIO_CONFIG_PE_MSK)
/* Also enable high drive strength */
#define KINETIS_GPIO_CONFIG_DSE(mux) \
(KINETIS_GPIO_CONFIG_MUX(mux) | KINETIS_GPIO_CONFIG_DSE_MSK)
/* /*
* TBD: similar macros with more options * TBD: similar macros with more options
*/ */
......
...@@ -98,6 +98,10 @@ ...@@ -98,6 +98,10 @@
#define KINETIS_FLEXBUS_CLK_DIV 3 #define KINETIS_FLEXBUS_CLK_DIV 3
/* Flash clock divider: 120/5 = 24 MHz */ /* Flash clock divider: 120/5 = 24 MHz */
#define KINETIS_FLASH_CLK_DIV 5 #define KINETIS_FLASH_CLK_DIV 5
/* NFC clock divider: PLL0/5 = 120/5 = 24 MHz */
#define KINETIS_NFCCLK_DIV 5
/* NFC clock fraction: do no multiply */
#define KINETIS_NFCCLK_FRAC 1
/* PLL input divider: 50/5 = 10 MHz */ /* PLL input divider: 50/5 = 10 MHz */
#define KINETIS_PLL_PRDIV 5 #define KINETIS_PLL_PRDIV 5
/* PLL multiplier: 10*24/2 = 120 MHz */ /* PLL multiplier: 10*24/2 = 120 MHz */
...@@ -147,8 +151,8 @@ ...@@ -147,8 +151,8 @@
* SRAM_U: 0x20000000 - 0x2000FFFF (64 kB) * SRAM_U: 0x20000000 - 0x2000FFFF (64 kB)
*/ */
#define CONFIG_MEM_RAM_BASE 0x1FFF0000 #define CONFIG_MEM_RAM_BASE 0x1FFF0000
#define CONFIG_MEM_RAM_LEN (22 * 1024) #define CONFIG_MEM_RAM_LEN (32 * 1024)
#define CONFIG_MEM_RAM_BUF_LEN (84 * 1024) #define CONFIG_MEM_RAM_BUF_LEN (74 * 1024)
#define CONFIG_MEM_MALLOC_LEN (18 * 1024) #define CONFIG_MEM_MALLOC_LEN (18 * 1024)
#define CONFIG_MEM_STACK_LEN (4 * 1024) #define CONFIG_MEM_STACK_LEN (4 * 1024)
/* /*
...@@ -171,16 +175,23 @@ ...@@ -171,16 +175,23 @@
/* /*
* Configuration of the external Flash memory * Configuration of the external Flash memory
*/ */
/* No NOR flash present */
#define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_NO_FLASH
/* NAND Flash configuration */
#define CONFIG_NAND_FSL_NFC
#define CONFIG_SYS_NAND_BASE 0x400A8000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
/* /*
* Store env in memory only * Store environment in the NAND Flash
*/ */
#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE (4 * 1024) #define CONFIG_ENV_OFFSET 0
#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BANK1_BASE #define CONFIG_ENV_SIZE 0x20000
#define CONFIG_INFERNO 1 #define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_OVERWRITE 1
/* /*
* Serial console configuration * Serial console configuration
...@@ -286,6 +297,7 @@ ...@@ -286,6 +297,7 @@
#undef CONFIG_CMD_NFS #undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE #undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG #undef CONFIG_CMD_XIMG
#define CONFIG_CMD_NAND
/* /*
* To save memory disable long help * To save memory disable long help
......
...@@ -16,45 +16,6 @@ ...@@ -16,45 +16,6 @@
#define MPC5125_NFC_H #define MPC5125_NFC_H