Commit 7eda904f authored by Sergei Poselenov's avatar Sergei Poselenov
Browse files

RT #73025. Moved Cortex-M3 core-specific definitions to asm/arch-cortexm3/hardware.h.

Little code cleanup for CM3 and A2F targets.
parent 4cae92da
......@@ -21,7 +21,6 @@
#include <common.h>
#include "clock.h"
#include "asm/arch-a2f/a2f.h"
/*
* Print the CPU specific information
......@@ -47,12 +46,14 @@ void __attribute__((section(".ramcode")))
__attribute__ ((long_call))
reset_cpu(ulong addr)
{
volatile struct cm3_scb *scb = (volatile struct cm3_scb *)CM3_SCB_BASE;
/*
* Perform reset but keep priority group unchanged.
*/
A2F_SCB->aircr = (0x5FA << 16) |
(A2F_SCB->aircr & (7<<8)) |
(1<<2);
scb->aircr = (CM3_AIRCR_VECTKEY << CM3_AIRCR_VECTKEY_SHIFT) |
(scb->aircr &
(CM3_AIRCR_PRIGROUP_MSK << CM3_AIRCR_PRIGROUP_SHIFT)) |
CM3_AIRCR_SYSRESET;
}
/*
......@@ -60,5 +61,6 @@ void __attribute__((section(".ramcode")))
*/
unsigned char cortex_m3_irq_vec_get(void)
{
return A2F_SCB->icsr & 0xFF;
volatile struct cm3_scb *scb = (volatile struct cm3_scb *)CM3_SCB_BASE;
return scb->icsr & CM3_ICSR_VECTACT_MSK;
}
/*
* (C) Copyright 2010,2011
*
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com
*
* This program is free software; you can redistribute it and/or
......@@ -15,62 +14,59 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
struct systick {
uint32_t ctrl; /* Control and Status Register */
uint32_t load; /* Reload Value Register */
uint32_t val; /* Current Value Register */
uint32_t cal; /* Calibration Register */
};
/* system core clock /32 */
#define CONFIG_SYSTICK_FREQ 3125000
/* SysTick Base Address */
#define A2F_SYSTICK_BASE (A2F_SCS_BASE + 0x0010)
#define A2F_SYSTICK ((volatile struct systick *)(A2F_SYSTICK_BASE))
#define SYSTICK_LOAD_RELOAD_POS 0
#define SYSTICK_CTRL_ENABLE_POS 0
#define SYSTICK_LOAD_RELOAD_MSK (0xFFFFFFul << SYSTICK_LOAD_RELOAD_POS)
#define SYSTICK_CTRL_ENABLE_MSK (1ul << SYSTICK_CTRL_ENABLE_POS)
/* Internal tick units */
static unsigned long long timestamp; /* Monotonic incrementing timer */
static unsigned long lastdec; /* Last decrementer snapshot */
static unsigned long long timestamp; /* Monotonic incrementing timer */
static ulong lastdec; /* Last decrementer snapshot */
int timer_init()
{
A2F_SYSREG->soft_rst_cr &= ~(1 << 6); /* Release systimer from reset */
A2F_TIMER->timer64_mode = 0; /* enable 32bit timer1 */
A2F_TIMER->timer1_ctrl = 0x03; /* timer1 is used by envm driver */
A2F_SYSREG->systick_cr &= ~(1 << 25); /* en noref */
A2F_SYSREG->systick_cr |= (3 << 28); /* div by 32 */
A2F_SYSREG->systick_cr &= ~0xffffff;
A2F_SYSREG->systick_cr |= 0x7a12;
A2F_SYSTICK->load = SYSTICK_LOAD_RELOAD_MSK - 1;
A2F_SYSTICK->val = 0;
volatile struct a2f_sysreg *a2f_sysreg =
(volatile struct a2f_sysreg *)A2F_SYSREG_BASE;
volatile struct a2f_timer *a2f_timer =
(volatile struct a2f_timer *)A2F_TIMER_BASE;
volatile struct cm3_systick *systick =
(volatile struct cm3_systick *)CM3_SYSTICK_BASE;
/* Release systimer from reset */
a2f_sysreg->soft_rst_cr &= ~A2F_SOFT_RST_TIMER_SR;
/* enable 32bit timer1 */
a2f_timer->timer64_mode &= ~A2F_TIM64_64MODE_EN;
/* timer1 is used by envm driver */
a2f_timer->timer1_ctrl = A2F_TIM_CTRL_MODE_ONESHOT|A2F_TIM_CTRL_EN;
/* No reference clock */
a2f_sysreg->systick_cr &= ~A2F_SYSTICK_NOREF;
/* div by 32 */
a2f_sysreg->systick_cr |= (A2F_SYSTICK_STCLK_DIV_32 <<
A2F_SYSTICK_STCLK_DIV_SHIFT);
a2f_sysreg->systick_cr &= ~A2F_SYSTICK_TENMS_MSK;
a2f_sysreg->systick_cr |= 0x7a12;
systick->load = CM3_SYSTICK_LOAD_RELOAD_MSK - 1;
systick->val = 0;
/* we don't want ints to be enabled */
A2F_SYSTICK->ctrl = SYSTICK_CTRL_ENABLE_MSK;
systick->ctrl = CM3_SYSTICK_CTRL_EN;
timestamp = 0;
return 0;
}
unsigned long get_timer(unsigned long base)
ulong get_timer(ulong base)
{
unsigned long now = A2F_SYSTICK->val;
volatile struct cm3_systick *systick =
(volatile struct cm3_systick *)CM3_SYSTICK_BASE;
ulong now = systick->val;
if (lastdec >= now)
timestamp += lastdec - now;
else
timestamp += lastdec + SYSTICK_LOAD_RELOAD_MSK - 1 - now;
timestamp += lastdec + CM3_SYSTICK_LOAD_RELOAD_MSK - 1 - now;
lastdec = now;
......@@ -79,27 +75,32 @@ unsigned long get_timer(unsigned long base)
void reset_timer(void)
{
lastdec = A2F_SYSTICK->val;
volatile struct cm3_systick *systick =
(volatile struct cm3_systick *)(CM3_SYSTICK_BASE);
lastdec = systick->val;
timestamp = 0;
}
/* delay x useconds */
void __udelay(unsigned long usec)
void __udelay(ulong usec)
{
unsigned long clc, tmp;
ulong clc, tmp;
volatile struct cm3_systick *systick =
(volatile struct cm3_systick *)(CM3_SYSTICK_BASE);
clc = usec * (CONFIG_SYSTICK_FREQ / 1000000);
/* get current timestamp */
tmp = A2F_SYSTICK->val;
tmp = systick->val;
if (tmp < clc) {
/* loop till event */
while (A2F_SYSTICK->val < tmp ||
A2F_SYSTICK->val > (SYSTICK_LOAD_RELOAD_MSK - 1 -
while (systick->val < tmp ||
systick->val > (CM3_SYSTICK_LOAD_RELOAD_MSK - 1 -
clc + tmp)) ; /* nop */
} else {
while (A2F_SYSTICK->val > (tmp - clc)) ;
while (systick->val > (tmp - clc)) ;
}
}
......@@ -107,7 +108,7 @@ void __udelay(unsigned long usec)
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
unsigned long get_tbclk(void)
ulong get_tbclk(void)
{
return CONFIG_SYSTICK_FREQ;
}
......@@ -20,7 +20,6 @@
*/
#include <common.h>
#include <asm/arch/stm32f2.h>
#include "clock.h"
......
......@@ -66,21 +66,17 @@ struct a2f_sysreg {
unsigned int iomux_cr[83];
};
#define A2F_SYSREG_BASE 0xE0042000
#define A2F_SYSREG ((volatile struct a2f_sysreg *)(A2F_SYSREG_BASE))
#define A2F_SYSREG_BASE 0xE0042000
#define A2F_SYSREG ((volatile struct a2f_sysreg *)(A2F_SYSREG_BASE))
struct a2f_scb {
unsigned int cpuid;
unsigned int icsr;
unsigned int vtor;
unsigned int aircr;
};
#define A2F_SCB_BASE 0xE000ED00
#define A2F_SCB ((volatile struct a2f_scb *)(A2F_SCB_BASE))
#define A2F_SOFT_RST_TIMER_SR (1<<6)
#define A2F_SCS_BASE 0xE000E000
#define A2F_SYSTICK_NOREF (1<<25)
#define A2F_SYSTICK_STCLK_DIV_SHIFT 28
#define A2F_SYSTICK_STCLK_DIV_32 3
#define A2F_SYSTICK_TENMS_MSK (0x00FFFFFF)
#define A2F_SCS_BASE 0xE000E000
struct a2f_timer
{
......@@ -110,9 +106,13 @@ struct a2f_timer
unsigned int timer64_mode;
};
#define A2F_TIMER_BASE 0x40005000
#define A2F_TIMER_BASE 0x40005000
#define A2F_TIMER ((volatile struct a2f_timer *)(A2F_TIMER_BASE))
#define A2F_TIM64_64MODE_EN 1
#define A2F_TIM_CTRL_MODE_ONESHOT 2
#define A2F_TIM_CTRL_EN 1
/*
* Clocks enumeration.
*/
......
/*
* (C) Copyright 2011
* Sergei Poselenov, Emcraft systems, sposelenov@emcraft.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Cortex M3 common definitions - SCB, NVIC, System Timer, MPU.
*/
#ifndef _ARCH_HWCM3_H_
#define _ARCH_HWCM3_H_
/* SCB Base Address */
#define CM3_SCB_BASE 0xE000ED00
struct cm3_scb {
uint32_t cpuid; /* CPUID Base Register */
uint32_t icsr; /* Interrupt Control and State Register */
uint32_t vtor; /* Vector Table Offset Register */
uint32_t aircr; /* App Interrupt and Reset Control Register */
};
#define CM3_AIRCR_VECTKEY 0x5fa
#define CM3_AIRCR_VECTKEY_SHIFT 16
#define CM3_AIRCR_ENDIAN (1<<15)
#define CM3_AIRCR_PRIGROUP_MSK 0x7
#define CM3_AIRCR_PRIGROUP_SHIFT 8
#define CM3_AIRCR_SYSRESET (1<<2)
#define CM3_ICSR_VECTACT_MSK 0xFF
/* SysTick Base Address */
#define CM3_SYSTICK_BASE 0xE000E010
struct cm3_systick {
uint32_t ctrl; /* Control and Status Register */
uint32_t load; /* Reload Value Register */
uint32_t val; /* Current Value Register */
uint32_t cal; /* Calibration Register */
};
#define CM3_SYSTICK_LOAD_RELOAD_MSK (0x00FFFFFF)
#define CM3_SYSTICK_CTRL_EN 1
#endif
......@@ -110,9 +110,15 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_SOC_DA8XX
#include <asm/arch/hardware.h>
#endif
#ifdef CONFIG_SYS_ARMCORTEXM3
#include <asm/arch-cortexm3/hardware.h>
#endif
#ifdef CONFIG_SYS_A2F
#include <asm/arch-a2f/a2f.h>
#endif
#ifdef CONFIG_SYS_STM32F2
#include <asm/arch-stm32f2/stm32f2.h>
#endif
#include <part.h>
#include <flash.h>
......
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