Commit 86eed375 authored by Pavel Boldin's avatar Pavel Boldin

RT100220 Hitex LPC4350 RMII mode, lower frequency

parent 1849bb73
......@@ -187,6 +187,7 @@ static const struct lpc18xx_pin_config hitex_lpc4350_iomux[] = {
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 1, 0)},
#ifdef CONFIG_LPC18XX_ETH
# ifndef CONFIG_LPC18XX_ENET_USE_PHY_RMII
/*
* Pin configuration for Ethernet (MII + MDIO)
*/
......@@ -226,6 +227,29 @@ static const struct lpc18xx_pin_config hitex_lpc4350_iomux[] = {
{{0x1, 19}, LPC18XX_IOMUX_CONFIG(0, 0, 1, 0, 1, 1)},
/* P1.16 = ENET_RXDV */
{{0x1, 16}, LPC18XX_IOMUX_CONFIG(7, 0, 1, 0, 1, 1)},
# else /* CONFIG_LPC18XX_ENET_USE_PHY_RMII */
/*
* Pin configuration for Ethernet (RMII + MDIO)
*/
/* PC.1 = ENET_MDC */
{{0xC, 1}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 0, 1, 1)},
/* P1.17 = ENET_MDIO (high-drive pin) */
{{0x1, 17}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 0, 1, 1)},
/* P1.18 = ENET_TXD0 */
{{0x1, 18}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 0, 1, 1)},
/* P1.20 = ENET_TXD1 */
{{0x1, 20}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 0, 1, 1)},
/* P0.1 = ENET_TX_EN */
{{0x0, 1}, LPC18XX_IOMUX_CONFIG(6, 0, 0, 0, 1, 1)},
/* P1.15 = ENET_RXD0 */
{{0x1, 15}, LPC18XX_IOMUX_CONFIG(3, 0, 0, 0, 1, 1)},
/* P0.0 = ENET_RXD1 */
{{0x0, 0}, LPC18XX_IOMUX_CONFIG(2, 0, 0, 0, 1, 1)},
/* P1.19 = ENET_REF_CLK */
{{0x1, 19}, LPC18XX_IOMUX_CONFIG(0, 0, 0, 0, 1, 1)},
/* P1.16 = ENET_RXDV */
{{0x1, 16}, LPC18XX_IOMUX_CONFIG(7, 0, 0, 0, 1, 1)},
# endif /* CONFIG_LPC18XX_ENET_USE_PHY_RMII */
#endif /* CONFIG_LPC18XX_ETH */
#if defined(CONFIG_NR_DRAM_BANKS) || defined(CONFIG_SYS_FLASH_CS)
......
......@@ -516,6 +516,16 @@ static int lpc18xx_phy_link_setup(struct lpc18xx_eth_dev *mac)
int rv, timeout;
int link_up, full_dup, speed;
#if defined(CONFIG_LPC18XX_PHY_RMII_REG) && defined(CONFIG_LPC18XX_PHY_RMII_MASK)
rv = lpc18xx_phy_read(mac, CONFIG_LPC18XX_PHY_RMII_REG, &bmsr);
if (rv != 0)
goto out;
bmsr |= CONFIG_LPC18XX_PHY_RMII_MASK;
rv = lpc18xx_phy_write(mac, CONFIG_LPC18XX_PHY_RMII_REG, bmsr);
if (rv != 0)
goto out;
#endif
rv = lpc18xx_phy_read(mac, PHY_BMSR, &bmsr);
if (rv != 0)
goto out;
......
......@@ -87,7 +87,7 @@
/*
* PLL1 multiplier value (1..256)
*/
#define CONFIG_LPC18XX_PLL1_M 17 /* 12 MHz * 17 = 204 MHz */
#define CONFIG_LPC18XX_PLL1_M 15 /* 12 MHz * 15 = 180 MHz */
/*
* Number of clock ticks in 1 sec
......@@ -273,6 +273,9 @@
#define CONFIG_NET_MULTI
#define CONFIG_LPC18XX_ETH
#define CONFIG_LPC18XX_ETH_DIV_SEL 4 /* 150-250 MHz */
#define CONFIG_LPC18XX_ENET_USE_PHY_RMII
#define CONFIG_LPC18XX_PHY_RMII_REG 0x17
#define CONFIG_LPC18XX_PHY_RMII_MASK (1<<5)
/*
* Ethernet RX buffers are malloced from the internal SRAM (more precisely,
......
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