Skip to content

GitLab

Commit 8a0aafd0 authored by Dmitry Konyshev's avatar Dmitry Konyshev
Browse files

Revert "RT #74863. Rolled back the "LCD" commit as it causes the flash problems." 

This reverts commit 1ddfff86.
parent c4bedbf5
Hide whitespace changes
Inline Side-by-side
board/stm/stm3220g-eval/board.c
View file @ 8a0aafd0
......@@ -25,9 +25,11 @@
#include <common.h>
#include <netdev.h>
#include <ili932x.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32f2_gpio.h>
#include <asm/arch/fsmc.h>
#if (CONFIG_NR_DRAM_BANKS > 0)
/*
......@@ -35,108 +37,38 @@
*/
# if !defined(CONFIG_SYS_RAM_CS) || !defined(CONFIG_SYS_FSMC_PSRAM_BCR) || \
!defined(CONFIG_SYS_FSMC_PSRAM_BTR)
# error "Incorrect FSMC configuration."
# error "Incorrect PSRAM FSMC configuration."
# endif
#endif /* CONFIG_NR_DRAM_BANKS */
/*
* STM32 RCC FSMC specific definitions
*/
#define STM32_RCC_ENR_FSMC (1 << 0) /* FSMC module clock */
DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_NR_DRAM_BANKS > 0) || !defined(CONFIG_SYS_NO_FLASH)
/*
* External SRAM GPIOs for FSMC:
*
* D0..D15, A0..A23, NE2/1, NOE, NWE, NBL1/0, CLK, NL, NWAIT
*/
static struct stm32f2_gpio_dsc fsmc_gpio[] = {
{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_7},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_0},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_1},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_4},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_5},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_6},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_7},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_8},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_9},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_10},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_11},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_12},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_13},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_14},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_15},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_0},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_1},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_2},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_4},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_5},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_6},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_7},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_8},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_9},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_10},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_11},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_12},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_13},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_14},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_15},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_0},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_1},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_2},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_4},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_5},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_12},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_13},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_14},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_15},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_0},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_1},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_2},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_4},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_5},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_9}
};
#endif
/*
* Early hardware init.
*/
int board_init(void)
{
int rv = 0;
#if (CONFIG_NR_DRAM_BANKS > 0) || !defined(CONFIG_SYS_NO_FLASH)
/*
* Some external memory is used. Connect GPIOs to FSMC controller
*/
int i;
int rv;
for (i = 0; i < sizeof(fsmc_gpio)/sizeof(fsmc_gpio[0]); i++) {
rv = stm32f2_gpio_config(&fsmc_gpio[i],
STM32F2_GPIO_ROLE_FSMC);
if (rv != 0)
break;
}
#if !defined(CONFIG_SYS_NO_FLASH)
if ((rv = fsmc_nor_psram_init(CONFIG_SYS_FLASH_CS, CONFIG_SYS_FSMC_FLASH_BCR,
CONFIG_SYS_FSMC_FLASH_BTR,
CONFIG_SYS_FSMC_FLASH_BWTR)))
return rv;
#endif
#if defined(CONFIG_LCD)
/*
* Enable FSMC interface clock
* Configure FSMC for accessing the LCD controller
*/
if (rv == 0)
STM32_RCC->ahb3enr |= STM32_RCC_ENR_FSMC;
if ((rv = fsmc_nor_psram_init(CONFIG_LCD_CS, CONFIG_LCD_FSMC_BCR,
CONFIG_LCD_FSMC_BTR, CONFIG_LCD_FSMC_BWTR)))
return rv;
gd->fb_base = CONFIG_FB_ADDR;
#endif
return rv;
return 0;
}
/*
......@@ -150,65 +82,26 @@ int checkboard(void)
return 0;
}
#ifdef CONFIG_MISC_INIT_R
/*
* Configure board specific parts.
*/
int misc_init_r(void)
{
#if !defined(CONFIG_SYS_NO_FLASH)
int i, rv;
/*
* Configure FSMC Flash block
*/
i = CONFIG_SYS_FLASH_CS - 1;
/*
* FIXME: not sure if this fake read is necessary here
*/
rv = STM32_FSMC->cs[i].bcr;
STM32_FSMC->cs[i].bcr = CONFIG_SYS_FSMC_FLASH_BCR;
STM32_FSMC->cs[i].btr = CONFIG_SYS_FSMC_FLASH_BTR;
# if defined(CONFIG_SYS_FSMC_FLASH_BWTR)
STM32_FSMC->wt[i].bwtr = CONFIG_SYS_FSMC_FLASH_BWTR;
# endif
#endif /* CONFIG_SYS_NO_FLASH */
return 0;
}
#endif
/*
* Setup external RAM.
*/
int dram_init(void)
{
int rv = 0;
#if (CONFIG_NR_DRAM_BANKS > 0)
static struct stm32f2_gpio_dsc ctrl_gpio = {STM32F2_GPIO_PORT_I,
STM32F2_GPIO_PIN_9};
int i;
/*
* Configure FSMC PSRAM block
*/
i = CONFIG_SYS_RAM_CS - 1;
/*
* Fake BCR read; if don't do this, then BCR remains configured
* with defaults.
*/
rv = STM32_FSMC->cs[i].bcr;
/* Step.1 */
STM32_FSMC->cs[i].bcr = CONFIG_SYS_FSMC_PSRAM_BCR;
STM32_FSMC->cs[i].btr = CONFIG_SYS_FSMC_PSRAM_BTR;
# if defined(CONFIG_SYS_FSMC_PSRAM_BWTR)
STM32_FSMC->wt[i].bwtr = CONFIG_SYS_FSMC_PSRAM_BWTR;
# endif
int rv = 0;
rv = fsmc_nor_psram_init(CONFIG_SYS_RAM_CS,
CONFIG_SYS_FSMC_PSRAM_BCR,
CONFIG_SYS_FSMC_PSRAM_BTR,
#ifdef CONFIG_SYS_FSMC_PSRAM_BWTR
CONFIG_SYS_FSMC_PSRAM_BWTR
#else
(u32)-1
#endif
);
if (rv != 0)
goto out;
rv = stm32f2_gpio_config(&ctrl_gpio, STM32F2_GPIO_ROLE_GPOUT);
if (rv != 0)
......@@ -229,16 +122,15 @@ int dram_init(void)
stm32f2_gpout_set(&ctrl_gpio, 0);
/* Step.6 */
STM32_FSMC->cs[i].bcr = 0x00083115;
STM32_FSMC->cs[i].btr = 0x0010FFFF;
fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115,
0x0010FFFF, -1);
/* Step.7 */
rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x000000);
/* Step.8 */
STM32_FSMC->cs[i].bcr = 0x00005059;
STM32_FSMC->cs[i].btr = 0x10000702;
STM32_FSMC->wt[i].bwtr = 0x10000602;
fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00005059,
0x10000702, 0x10000602);
/* Step.9 */
stm32f2_gpout_set(&ctrl_gpio, 1);
......@@ -250,8 +142,8 @@ int dram_init(void)
stm32f2_gpout_set(&ctrl_gpio, 0);
/* Step.12 */
STM32_FSMC->cs[i].bcr = 0x00083115;
STM32_FSMC->cs[i].btr = 0x0010FFFF;
fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115,
0x0010FFFF, -1);
/* Step.13 */
rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x01000000);
......@@ -270,9 +162,8 @@ int dram_init(void)
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
rv = 0;
out:
#endif /* CONFIG_NR_DRAM_BANKS */
return rv;
}
......
common/lcd.c
View file @ 8a0aafd0
......@@ -53,6 +53,10 @@
#include <atmel_lcdc.h>
#endif
#if defined(CONFIG_LCD_ILI932x)
#include <ili932x.h>
#endif
/************************************************************************/
/* ** FONT DATA */
/************************************************************************/
......@@ -786,6 +790,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
break;
};
#ifdef CONFIG_LCD_ILI932x
ili932x_update();
#endif
return (0);
}
#endif
......
cpu/arm_cortexm3/stm32/Makefile
View file @ 8a0aafd0
......@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS := clock.o cpu.o envm.o wdt.o
COBJS := clock.o cpu.o envm.o wdt.o fsmc.o
SOBJS :=
SRCS := $(COBJS:.o=.c)
......
cpu/arm_cortexm3/stm32/fsmc.c 0 → 100644
View file @ 8a0aafd0
/*
* (C) Copyright 2010,2011
* Dmitry Konyshev, Emcraft Systems, probables@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32f2_gpio.h>
/*
* STM32 RCC FSMC specific definitions
*/
#define STM32_RCC_ENR_FSMC (1 << 0) /* FSMC module clock */
/*
* FSMC registers base
*/
#define STM32_FSMC_BASE 0xA0000000
#define STM32_FSMC ((volatile struct stm32_fsmc_regs *) \
STM32_FSMC_BASE)
/*
* FSMC NOR/PSRAM controller register map
*/
struct stm32_fsmc_regs {
struct {
u32 bcr; /* Chip-select control */
u32 btr; /* Chip-select timing */
} cs[4];
u32 rsv0[57];
struct {
u32 bwtr; /* Write timing */
u32 rsv1;
} wt[4];
};
/*
* External SRAM GPIOs for FSMC:
*
* D0..D15, A0..A23, NOE, NWE, NBL1/0, CLK, NL, NWAIT
*/
static const struct stm32f2_gpio_dsc fsmc_gpio[] = {
{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_7},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_0},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_1},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_4},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_5},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_6},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_8},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_9},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_10},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_11},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_12},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_13},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_14},
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_15},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_0},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_1},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_2},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_4},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_5},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_6},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_7},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_8},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_9},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_10},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_11},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_12},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_13},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_14},
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_15},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_0},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_1},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_2},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_4},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_5},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_12},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_13},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_14},
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_15},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_0},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_1},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_2},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_3},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_4},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_5},
};
int fsmc_nor_psram_init(u32 num, u32 bcr, u32 btr, u32 bwtr)
{
int rv = 0;
static int common_init_done = 0;
static const struct stm32f2_gpio_dsc fsmc_cs[] = {
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_7},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_9},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_10},
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_12},
};
num--;
if (num > 3)
return -1;
if (!common_init_done) {
int i;
/*
* Connect GPIOs to FSMC controller
*/
for (i = 0; i < sizeof(fsmc_gpio)/sizeof(fsmc_gpio[0]); i++) {
rv = stm32f2_gpio_config(&fsmc_gpio[i],
STM32F2_GPIO_ROLE_FSMC);
if (rv != 0)
goto out;
}
/*
* Enable FSMC interface clock
*/
STM32_RCC->ahb3enr |= STM32_RCC_ENR_FSMC;
common_init_done = 1;
}
rv = stm32f2_gpio_config(&fsmc_cs[num], STM32F2_GPIO_ROLE_FSMC);
if (rv != 0)
goto out;
/*
* Fake BCR read; if don't do this, then BCR remains configured
* with defaults.
*/
rv = STM32_FSMC->cs[num].bcr;
STM32_FSMC->cs[num].btr = btr;
if (bwtr != (u32)-1)
STM32_FSMC->wt[num].bwtr = bwtr;
STM32_FSMC->cs[num].bcr = bcr;
rv = 0;
out:
return rv;
}
drivers/gpio/stm32f2_gpio.c
View file @ 8a0aafd0
......@@ -138,7 +138,7 @@ static const u32 af_val[STM32F2_GPIO_ROLE_LAST] = {
* Configure the specified GPIO for the specified role
* Returns 0 on success, -EINVAL otherwise.
*/
s32 stm32f2_gpio_config(struct stm32f2_gpio_dsc *dsc,
s32 stm32f2_gpio_config(const struct stm32f2_gpio_dsc *dsc,
enum stm32f2_gpio_role role)
{
volatile struct stm32f2_gpio_regs *gpio_regs;
......@@ -248,7 +248,7 @@ out:
* Set GPOUT to the state specified (1, 0).
* Returns 0 on success, -EINVAL otherwise.
*/
s32 stm32f2_gpout_set(struct stm32f2_gpio_dsc *dsc, int state)
s32 stm32f2_gpout_set(const struct stm32f2_gpio_dsc *dsc, int state)
{
volatile struct stm32f2_gpio_regs *gpio_regs;
s32 rv;
......
drivers/video/Makefile
View file @ 8a0aafd0
......@@ -38,6 +38,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
COBJS-$(CONFIG_LCD_ILI932x) += ili932x.o
COBJS-y += videomodes.o
COBJS := $(COBJS-y)
......
drivers/video/ili932x.c 0 → 100644
View file @ 8a0aafd0
/*
* (C) Copyright 2011
* Dmitry Konyshev, Emcraft Systems, probables@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <lcd.h>
#include <ili932x.h>
#ifdef CONFIG_LCD_ILI932x
#define XRES 320
#define YRES 240
#define BIT_PER_PIXEL 16
vidinfo_t panel_info = {
vl_col: XRES,
vl_row: YRES,
vl_bpix: 4,
};
void *lcd_base; /* Start of framebuffer memory */
void *lcd_console_address; /* Start of console buffer */
int lcd_line_length;
int lcd_color_fg;
int lcd_color_bg;
short console_col;
short console_row;
static volatile u16 *ili932x_reg = NULL;
static volatile u16 *ili932x_ram = NULL;
static u16 ili932x_read_reg(u8 reg)
{
*ili932x_reg = reg;
return *ili932x_ram;
}
static void ili932x_write_reg(u8 reg, u16 val)
{
*ili932x_reg = reg;
*ili932x_ram = val;
}
void lcd_enable(void)
{
/* Display On */
ili932x_write_reg(7, 0x0173); /* 262K color and display ON */
}
void lcd_disable(void)
{
/* Display Off */
ili932x_write_reg(7, 0); /* 262K color and display ON */
}
ulong calc_fbsize(void)
{
#ifdef CONFIG_LCD_ILI932x_DOUBLE_BUFFER
int buffers_cnt = 2;
#else
int buffers_cnt = 1;
#endif
return ((panel_info.vl_col * panel_info.vl_row *
NBITS(panel_info.vl_bpix)) / 8) * buffers_cnt;
}
int overwrite_console(void)
{
/* Keep stdout / stderr on serial, our LCD is for splashscreen only */
return 1;
}
void ili932x_update(void)
{
u16 *b = lcd_base;
int i;
ili932x_write_reg(32, 0);
ili932x_write_reg(33, 319);
*ili932x_reg = 34;
for (i = 0; i < XRES * YRES; i++) {
*ili932x_ram = *b++;
}
}
void lcd_ctrl_init(void *lcdbase)
{
u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8;
ili932x_reg = (volatile u16 *)CONFIG_LCD_ILI932x_BASE;
ili932x_ram = (volatile u16 *)CONFIG_LCD_ILI932x_BASE + 1;
if (!lcdbase)
return;
if (ili932x_read_reg(0) != 0x9325)
return;
/*
* LCD controller initialization taken from the stm322xg_eval_lcd.c sample
*/
/* Start Initial Sequence ------------------------------------------------*/
ili932x_write_reg(0, 0x0001); /* Start internal OSC. */
ili932x_write_reg(1, 0x0100); /* Set SS and SM bit */
ili932x_write_reg(2, 0x0700); /* Set 1 line inversion */
ili932x_write_reg(3, 0x1018); /* Set GRAM write direction and BGR=1. */
ili932x_write_reg(4, 0x0000); /* Resize register */
ili932x_write_reg(8, 0x0202); /* Set the back porch and front porch */
ili932x_write_reg(9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */
ili932x_write_reg(10, 0x0000); /* FMARK function */
ili932x_write_reg(12, 0x0001); /* RGB interface setting */
ili932x_write_reg(13, 0x0000); /* Frame marker Position */
ili932x_write_reg(15, 0x0000); /* RGB interface polarity */
/* Power On sequence -----------------------------------------------------*/
ili932x_write_reg(16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
ili932x_write_reg(17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
ili932x_write_reg(18, 0x0000); /* VREG1OUT voltage */
ili932x_write_reg(19, 0x0000); /* VDV[4:0] for VCOM amplitude */
udelay(200000); /* Dis-charge capacitor power voltage (200ms) */
ili932x_write_reg(16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
ili932x_write_reg(17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
udelay(50000); /* Delay 50 ms */
ili932x_write_reg(18, 0x0139); /* VREG1OUT voltage */