Commit 8cdee17b authored by Sergei Poselenov's avatar Sergei Poselenov
Browse files

RT #72064. Renamed xxx_PERITH_BASE to xxx_PERIPH_BASE. Code cleanup.

parent 58eb57ac
......@@ -42,26 +42,26 @@ static u32 flash_bsize[] = {
/*
* Number of flash blocks for STM32F2x chips
*/
#define STM32_FLASH_BLOCKS (sizeof(flash_bsize)/sizeof(flash_bsize[0]))
#define STM32_FLASH_BLOCKS ARRAY_SIZE(flash_bsize)
/*
* Flash registers base
*/
#define STM32_FLASHREGS_BASE (STM32_AHB1PERITH_BASE + 0x3C00)
#define STM32_FLASHREGS_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
/*
* Flash register map
*/
struct stm32_flash_regs {
u32 acr; /* Access control */
u32 keyr; /* Key */
u32 optkeyr; /* Option key */
u32 sr; /* Status */
u32 cr; /* Control */
u32 optcr; /* Option control */
u32 acr; /* Access control */
u32 keyr; /* Key */
u32 optkeyr; /* Option key */
u32 sr; /* Status */
u32 cr; /* Control */
u32 optcr; /* Option control */
};
#define STM32_FLASH_REGS ((volatile struct stm32_flash_regs *) \
STM32_FLASHREGS_BASE)
#define STM32_FLASH_REGS ((volatile struct stm32_flash_regs *) \
STM32_FLASHREGS_BASE)
/*
* Flash CR definitions
......@@ -82,10 +82,10 @@ struct stm32_flash_regs {
/*
* Flash ACR definitions
*/
#define STM32_FLASH_ACR_LAT_BIT 0 /* Latency */
#define STM32_FLASH_ACR_LAT_BIT 0 /* Latency */
#define STM32_FLASH_ACR_LAT_MSK 0x7
#define STM32_FLASH_ACR_PRFTEN (1 << 8) /* Prefetch enable */
#define STM32_FLASH_ACR_ICEN (1 << 9) /* Instruction cache enable */
#define STM32_FLASH_ACR_PRFTEN (1 << 8) /* Prefetch enable */
#define STM32_FLASH_ACR_ICEN (1 << 9) /* Icache enable */
/*
* Flash KEYR definitions
......
......@@ -33,15 +33,15 @@
/*
* GPIO registers bases
*/
#define STM32F2_GPIOA_BASE (STM32_AHB1PERITH_BASE + 0x0000)
#define STM32F2_GPIOB_BASE (STM32_AHB1PERITH_BASE + 0x0400)
#define STM32F2_GPIOC_BASE (STM32_AHB1PERITH_BASE + 0x0800)
#define STM32F2_GPIOD_BASE (STM32_AHB1PERITH_BASE + 0x0C00)
#define STM32F2_GPIOE_BASE (STM32_AHB1PERITH_BASE + 0x1000)
#define STM32F2_GPIOF_BASE (STM32_AHB1PERITH_BASE + 0x1400)
#define STM32F2_GPIOG_BASE (STM32_AHB1PERITH_BASE + 0x1800)
#define STM32F2_GPIOH_BASE (STM32_AHB1PERITH_BASE + 0x1C00)
#define STM32F2_GPIOI_BASE (STM32_AHB1PERITH_BASE + 0x2000)
#define STM32F2_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
#define STM32F2_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
#define STM32F2_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
#define STM32F2_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
#define STM32F2_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
#define STM32F2_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
#define STM32F2_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
#define STM32F2_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
#define STM32F2_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
/*
* GPIO configuration mode
......@@ -135,13 +135,13 @@ static const u32 af_val[STM32F2_GPIO_ROLE_LAST] = {
/*
* Configure the specified GPIO for the specified role
*/
int stm32f2_gpio_config(struct stm32f2_gpio_dsc *dsc,
s32 stm32f2_gpio_config(struct stm32f2_gpio_dsc *dsc,
enum stm32f2_gpio_role role)
{
volatile struct stm32f2_gpio_regs *gpio_regs;
u32 otype, ospeed, pupd, mode, i;
int rv;
s32 rv;
/*
* Check params
......@@ -242,10 +242,10 @@ out:
/*
* Set GPOUT to the state specified (1, 0)
*/
int stm32f2_gpout_set(struct stm32f2_gpio_dsc *dsc, int state)
s32 stm32f2_gpout_set(struct stm32f2_gpio_dsc *dsc, int state)
{
volatile struct stm32f2_gpio_regs *gpio_regs;
int rv;
s32 rv;
if (!dsc || dsc->port > 8 || dsc->pin > 15) {
printf("%s: incorrect params %d.%d.\n", __func__,
......
......@@ -54,7 +54,7 @@
/*
* MAC registers base
*/
#define STM32_MAC_BASE (STM32_AHB1PERITH_BASE + 0x8000)
#define STM32_MAC_BASE (STM32_AHB1PERIPH_BASE + 0x8000)
/*
* MACCR reg fields
......@@ -141,7 +141,7 @@
/*
* STM32 SYSCFG definitions
*/
#define STM32_SYSCFG_BASE (STM32_APB2PERITH_BASE + 0x3800)
#define STM32_SYSCFG_BASE (STM32_APB2PERIPH_BASE + 0x3800)
/*
* PMC reg fields
......@@ -247,7 +247,8 @@ struct stm32_mac_regs {
u32 dmachtbar; /* DMA current host transmit buffer address */
u32 dmachrbar; /* DMA current host receive buffer address */
};
#define STM32_MAC ((volatile struct stm32_mac_regs *)STM32_MAC_BASE)
#define STM32_MAC ((volatile struct stm32_mac_regs *) \
STM32_MAC_BASE)
/*
* SYSCFG register map
......@@ -259,8 +260,8 @@ struct stm32_syscfg_regs {
u32 rsv0[2];
u32 cmpcr; /* Compensation cell control */
};
#define STM32_SYSCFG ((volatile struct stm32_syscfg_regs *) \
STM32_SYSCFG_BASE)
#define STM32_SYSCFG ((volatile struct stm32_syscfg_regs *) \
STM32_SYSCFG_BASE)
/*
* STM32 ETH Normal DMA buffer descriptors
......@@ -294,7 +295,7 @@ struct stm_eth_dev {
*/
volatile struct stm_eth_dma_bd tx_bd;
volatile struct stm_eth_dma_bd rx_bd[PKTBUFSRX];
int rx_bd_idx;
s32 rx_bd_idx;
/*
* ETH DMAed buffers:
......@@ -364,22 +365,22 @@ static struct stm32f2_gpio_dsc mac_gpio[] = {
/*
* Prototypes
*/
static int stm_eth_init(struct eth_device *dev, bd_t *bd);
static int stm_eth_send(struct eth_device *dev, volatile void *pkt, int len);
static int stm_eth_recv(struct eth_device *dev);
static s32 stm_eth_init(struct eth_device *dev, bd_t *bd);
static s32 stm_eth_send(struct eth_device *dev, volatile void *pkt, s32 len);
static s32 stm_eth_recv(struct eth_device *dev);
static void stm_eth_halt(struct eth_device *dev);
static int stm_phy_write(struct stm_eth_dev *mac, u16 reg, u16 val);
static int stm_phy_read(struct stm_eth_dev *mac, u16 reg, u16 *val);
static s32 stm_phy_write(struct stm_eth_dev *mac, u16 reg, u16 val);
static s32 stm_phy_read(struct stm_eth_dev *mac, u16 reg, u16 *val);
/*
* Initialize driver
*/
int stm32_eth_init(bd_t *bd)
s32 stm32_eth_init(bd_t *bd)
{
struct stm_eth_dev *mac;
struct eth_device *netdev;
int rv;
s32 rv;
mac = malloc(sizeof(struct stm_eth_dev));
if (!mac) {
......@@ -421,9 +422,9 @@ out:
/*
* Initialize PHY
*/
static int stm_phy_init(struct stm_eth_dev *mac)
static s32 stm_phy_init(struct stm_eth_dev *mac)
{
int i, rv;
s32 i, rv;
u16 val;
/*
......@@ -465,11 +466,11 @@ out:
/*
* Get link status
*/
static int stm_phy_link_get(struct stm_eth_dev *mac,
int *link_up, int *full_dup, int *speed)
static s32 stm_phy_link_get(struct stm_eth_dev *mac,
s32 *link_up, s32 *full_dup, s32 *speed)
{
u16 val;
int rv;
s32 rv;
rv = stm_phy_read(mac, PHY_BMSR, &val);
if (rv != 0)
......@@ -490,11 +491,11 @@ out:
/*
* Setup link status
*/
static int stm_phy_link_setup(struct stm_eth_dev *mac)
static s32 stm_phy_link_setup(struct stm_eth_dev *mac)
{
static int link_inited;
static s32 link_inited;
int link_up, full_dup, speed, rv, i;
s32 link_up, full_dup, speed, rv, i;
u32 cr_val;
u16 val;
......@@ -583,11 +584,11 @@ out:
/*
* Write PHY
*/
static int stm_phy_write(struct stm_eth_dev *mac, u16 reg, u16 val)
static s32 stm_phy_write(struct stm_eth_dev *mac, u16 reg, u16 val)
{
u16 adr = mac->phy_adr;
u32 tmp;
int rv;
s32 rv;
tmp = 0;
while ((STM32_MAC->macmiiar & STM32_MAC_MIIAR_MB) &&
......@@ -647,11 +648,11 @@ out:
/*
* Read PHY
*/
static int stm_phy_read(struct stm_eth_dev *mac, u16 reg, u16 *val)
static s32 stm_phy_read(struct stm_eth_dev *mac, u16 reg, u16 *val)
{
u16 adr = mac->phy_adr;
u32 tmp;
int rv;
s32 rv;
tmp = 0;
while ((STM32_MAC->macmiiar & STM32_MAC_MIIAR_MB) &&
......@@ -714,7 +715,7 @@ out:
*/
static void stm_mac_bd_init(struct stm_eth_dev *mac)
{
int i;
s32 i;
/*
* Init Tx buffer descriptor
......@@ -769,12 +770,12 @@ static void stm_mac_address_set(struct stm_eth_dev *mac)
/*
* Init GPIOs used by MAC
*/
static int stm_mac_gpio_init(struct stm_eth_dev *mac)
static s32 stm_mac_gpio_init(struct stm_eth_dev *mac)
{
static int gpio_inited;
static s32 gpio_inited;
u32 val;
int i, rv;
s32 i, rv;
/*
* Init GPIOs only once at start. Otherwise, reiniting then on
......@@ -821,10 +822,10 @@ out:
/*
* Init STM32 MAC hardware
*/
static int stm_mac_hw_init(struct stm_eth_dev *mac)
static s32 stm_mac_hw_init(struct stm_eth_dev *mac)
{
u32 tmp, hclk;
int i, rv;
s32 i, rv;
/*
* Init GPIOs
......@@ -924,10 +925,10 @@ out:
/*
* Init STM32 MAC and DMA
*/
static int stm_eth_init(struct eth_device *dev, bd_t *bd)
static s32 stm_eth_init(struct eth_device *dev, bd_t *bd)
{
struct stm_eth_dev *mac = to_stm_eth(dev);
int rv;
s32 rv;
/*
* Init hw
......@@ -976,10 +977,10 @@ out:
/*
* Send frame
*/
static int stm_eth_send(struct eth_device *dev, volatile void *pkt, int len)
static s32 stm_eth_send(struct eth_device *dev, volatile void *pkt, s32 len)
{
struct stm_eth_dev *mac = to_stm_eth(dev);
int rv, tout;
s32 rv, tout;
if (len > PKTSIZE_ALIGN) {
printf("%s: frame too long (%d).\n", __func__, len);
......@@ -1037,7 +1038,7 @@ out:
/*
* Process received frames (if any)
*/
static int stm_eth_recv(struct eth_device *dev)
static s32 stm_eth_recv(struct eth_device *dev)
{
volatile struct stm_eth_dma_bd *bd;
struct stm_eth_dev *mac = to_stm_eth(dev);
......
......@@ -78,12 +78,12 @@
/*
* USART registers bases
*/
#define STM32_USART1_BASE (STM32_APB2PERITH_BASE + 0x1000)
#define STM32_USART2_BASE (STM32_APB1PERITH_BASE + 0x4400)
#define STM32_USART3_BASE (STM32_APB1PERITH_BASE + 0x4800)
#define STM32_USART4_BASE (STM32_APB1PERITH_BASE + 0x4C00)
#define STM32_USART5_BASE (STM32_APB1PERITH_BASE + 0x5000)
#define STM32_USART6_BASE (STM32_APB2PERITH_BASE + 0x1400)
#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000)
#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400)
#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
#define STM32_USART4_BASE (STM32_APB1PERIPH_BASE + 0x4C00)
#define STM32_USART5_BASE (STM32_APB1PERIPH_BASE + 0x5000)
#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
/*
* SR bit masks
......@@ -193,7 +193,7 @@ static volatile struct stm32_usart_regs *usart_regs;
/*
* Initialize the serial port.
*/
int serial_init(void)
s32 serial_init(void)
{
static struct stm32f2_gpio_dsc tx_gpio = { USART_TX_IO_PORT,
USART_TX_IO_PIN };
......@@ -201,7 +201,7 @@ int serial_init(void)
USART_RX_IO_PIN };
static volatile u32 *usart_enr;
int rv;
s32 rv;
/*
* Setup registers
......@@ -289,7 +289,7 @@ void serial_setbrg(void)
/*
* Read a single character from the serial port.
*/
int serial_getc(void)
s32 serial_getc(void)
{
while (!(usart_regs->sr & STM32_USART_SR_RXNE));
......@@ -321,7 +321,7 @@ void serial_puts(const char *s)
/*
* Test whether a character in in the RX buffer.
*/
int serial_tstc(void)
s32 serial_tstc(void)
{
return (usart_regs->sr & STM32_USART_SR_RXNE) ? 1 : 0;
}
......@@ -30,10 +30,10 @@
******************************************************************************/
#define STM32_PERIPH_BASE 0x40000000
#define STM32_APB1PERITH_BASE (STM32_PERIPH_BASE + 0x00000000)
#define STM32_APB2PERITH_BASE (STM32_PERIPH_BASE + 0x00010000)
#define STM32_AHB1PERITH_BASE (STM32_PERIPH_BASE + 0x00020000)
#define STM32_AHB2PERITH_BASE (STM32_PERIPH_BASE + 0x10000000)
#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000)
/******************************************************************************
* Reset and Clock Control
......@@ -90,8 +90,9 @@ enum clock {
/*
* RCC registers base
*/
#define STM32_RCC_BASE (STM32_AHB1PERITH_BASE + 0x3800)
#define STM32_RCC ((volatile struct stm32_rcc_regs *)STM32_RCC_BASE)
#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
#define STM32_RCC ((volatile struct stm32_rcc_regs *) \
STM32_RCC_BASE)
/******************************************************************************
* Flexible static memory controller
......@@ -116,7 +117,8 @@ struct stm32_fsmc_regs {
* FSMC registers base
*/
#define STM32_FSMC_BASE 0xA0000000
#define STM32_FSMC ((volatile struct stm32_fsmc_regs *)STM32_FSMC_BASE)
#define STM32_FSMC ((volatile struct stm32_fsmc_regs *) \
STM32_FSMC_BASE)
/*
* BCR reg fields
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment