Commit 8dab5b72 authored by Vladimir Khusainov's avatar Vladimir Khusainov

RT92026 An optimization to the SDRAM timings in U-Boot on

the STM32F429 Discovery.
parent c17514d0
......@@ -188,7 +188,7 @@ static inline u32 _ns2clk(u32 ns, u32 freq)
/*
* Following are timings for IS42S16400J, from corresponding datasheet
*/
#define SDRAM_CAS 3
#define SDRAM_CAS 2
#define SDRAM_NB 1 /* Number of banks */
#define SDRAM_MWID 1 /* 16 bit memory */
......
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