Commit 957a77c0 authored by Sergei Poselenov's avatar Sergei Poselenov
Browse files

Merge branch 'master' of /SR/git/A2F/u-boot

parents 7eda904f ed5cc8ea
......@@ -24,6 +24,7 @@
*/
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -73,3 +74,14 @@ int dram_init(void)
return 0;
}
#ifdef CONFIG_STM32F2_ETH
/*
* Register ethernet driver
*/
int board_eth_init(bd_t *bis)
{
return stm32f2_eth_init(bis);
}
#endif
......@@ -27,13 +27,19 @@
*/
int print_cpuinfo(void)
{
printf("CPU: %s\n", "SmartFusion FPGA (Cortex-M3 Hard IP)");
#if defined(DEBUG)
printf("Frequencies: FCLK=%d, PCLK0=%d, PCLK1=%d, ACE=%d, FPGA=%d\n",
clock_get(CLOCK_FCLK), clock_get(CLOCK_PCLK0),
clock_get(CLOCK_PCLK1), clock_get(CLOCK_ACE),
clock_get(CLOCK_FPGA));
#endif
char buf[5][32];
printf("CPU : %s\n", "SmartFusion FPGA (Cortex-M3 Hard IP)");
strmhz(buf[0], clock_get(CLOCK_FCLK));
strmhz(buf[1], clock_get(CLOCK_PCLK0));
strmhz(buf[2], clock_get(CLOCK_PCLK1));
strmhz(buf[3], clock_get(CLOCK_ACE));
strmhz(buf[4], clock_get(CLOCK_FPGA));
printf("Freqs: FCLK=%sMHz,PCLK0=%sMHz,PCLK1=%sMHz,ACE=%sMHz,"
"FPGA=%sMHz\n",
buf[0], buf[1], buf[2], buf[3], buf[4]);
return 0;
}
......
......@@ -23,16 +23,24 @@
/*
* Initialize the eNVM interface
*/
extern void envm_init(void);
void envm_init(void);
/*
* Write a data buffer to eNVM.
* Note that we need for this function to reside in RAM since it
* will be used to self-upgrade U-boot in eNMV.
*/
extern unsigned int
unsigned int
__attribute__((section(".ramcode")))
__attribute__ ((long_call))
envm_write(unsigned int offset, void * buf, unsigned int size);
#if defined(CONFIG_SYS_STM32F2)
/*
* Enable instruction cache, prefetch and set the Flash wait latency
* according to the clock configuration used (HCLK value).
*/
void envm_config(u32 wait_states);
#endif /* CONFIG_SYS_STM32F2 */
#endif /* __ENVM_H__ */
......@@ -29,13 +29,9 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS := clock.o cpu.o envm.o timer.o wdt.o
SOBJS :=
COBJS-y := clock.o cpu.o envm.o timer.o wdt.o
COBJS-$(CONFIG_STM32F2_GPIO) += gpio.o
COBJS-$(CONFIG_STM32F2_USART_CONSOLE) += serial.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
......
......@@ -22,6 +22,7 @@
#include <common.h>
#include "clock.h"
#include "envm.h"
/*
* STM32F2 Clock configuration is set by the number of CONFIG options.
......@@ -198,60 +199,16 @@
#define STM32F2_RCC_PLLCFGR_PLLQ_BIT 24 /* Div factor for USB,SDIO,.. */
#define STM32F2_RCC_PLLCFGR_PLLQ_MSK 0xF
/*
* Flash registers base
*/
#define STM32F2_FLASH_BASE (STM32F2_AHB1PERITH_BASE + 0x3C00)
/*
* Flash ACR definitions
*/
#define STM32F2_FLASH_ACR_LAT_BIT 0 /* Latency */
#define STM32F2_FLASH_ACR_LAT_MSK 0x3
#define STM32F2_FLASH_ACR_PRFTEN (1 << 8) /* Prefetch enable */
#define STM32F2_FLASH_ACR_ICEN (1 << 9) /* Instruction cache enable*/
/*
* Timeouts (in cycles)
*/
#define STM32F2_HSE_STARTUP_TIMEOUT 0x0500
/*
* Flash register map
*/
struct stm32f2_flash_regs {
u32 acr; /* Access control */
u32 keyr; /* Key */
u32 optkeyr; /* Option key */
u32 sr; /* Status */
u32 cr; /* Control */
u32 optcr; /* Option control */
};
/*
* Clock values
*/
static u32 clock_val[CLOCK_END];
/*
* Enable instruction cache, prefetch and set the Flash wait latency
* according to the clock configuration used (HCLK value).
* We _must_ do this before changing System clock source (or will crash on
* fetching instructions of while() wait cycle).
* In case of HSI clock - no Sys clock change happens, but, for consistency,
* we configure Flash this way as well.
*/
static void flash_setup(void)
{
volatile struct stm32f2_flash_regs *flash_regs;
flash_regs = (struct stm32f2_flash_regs *)STM32F2_FLASH_BASE;
flash_regs->acr = STM32F2_FLASH_ACR_PRFTEN |
STM32F2_FLASH_ACR_ICEN |
(STM32F2_FLASH_WS << STM32F2_FLASH_ACR_LAT_BIT);
}
#if !defined(CONFIG_STM32F2_SYS_CLK_HSI)
/*
* Set-up clock configuration.
......@@ -350,7 +307,7 @@ static void clock_setup(void)
* Configure Flash prefetch, Instruction cache, and wait
* latency.
*/
flash_setup();
envm_config(STM32F2_FLASH_WS);
/*
* Change system clock source, and wait (infinite!) till it done
......@@ -387,7 +344,7 @@ void clock_init(void)
/*
* For consistency with !HSI configs, enable prefetch and cache
*/
flash_setup();
envm_config(STM32F2_FLASH_WS);
#endif
/*
......
......@@ -20,6 +20,7 @@
*/
#include <common.h>
#include <asm/arch/stm32f2.h>
#include "clock.h"
......@@ -28,13 +29,16 @@
*/
int print_cpuinfo(void)
{
printf("CPU: %s\n", "STM32 F2 series (Cortex-M3)");
char buf[4][32];
printf("CPU : %s\n", "STM32 F2 series (Cortex-M3)");
#if defined(DEBUG)
printf("Frequencies: SYSCLK=%d, HCLK=%d, PCLK1=%d, PCLK2=%d\n",
clock_get(CLOCK_SYSCLK), clock_get(CLOCK_HCLK),
clock_get(CLOCK_PCLK1), clock_get(CLOCK_PCLK2));
#endif
strmhz(buf[0], clock_get(CLOCK_SYSCLK));
strmhz(buf[1], clock_get(CLOCK_HCLK));
strmhz(buf[2], clock_get(CLOCK_PCLK1));
strmhz(buf[3], clock_get(CLOCK_PCLK2));
printf("Freqs: SYSCLK=%sMHz,HCLK=%sMHz,PCLK1=%sMHz,PCLK2=%sMHz\n",
buf[0], buf[1], buf[2], buf[3]);
return 0;
}
......
......@@ -20,9 +20,58 @@
*/
#include <common.h>
#include <asm/arch/stm32f2.h>
#include "envm.h"
/*
* Flash registers base
*/
#define STM32F2_FLASH_BASE (STM32F2_AHB1PERITH_BASE + 0x3C00)
/*
* Flash ACR definitions
*/
#define STM32F2_FLASH_ACR_LAT_BIT 0 /* Latency */
#define STM32F2_FLASH_ACR_LAT_MSK 0x3
#define STM32F2_FLASH_ACR_PRFTEN (1 << 8) /* Prefetch enable */
#define STM32F2_FLASH_ACR_ICEN (1 << 9) /* Instruction cache enable*/
/*
* Flash register map
*/
struct stm32f2_flash_regs {
u32 acr; /* Access control */
u32 keyr; /* Key */
u32 optkeyr; /* Option key */
u32 sr; /* Status */
u32 cr; /* Control */
u32 optcr; /* Option control */
};
/*
* Enable instruction cache, prefetch and set the Flash wait latency
* according to the clock configuration used (HCLK value).
* We _must_ do this before changing System clock source (or will crash on
* fetching instructions of while() wait cycle).
* In case of HSI clock - no Sys clock change happens, but, for consistency,
* we configure Flash this way as well.
*/
void envm_config(u32 wait_states)
{
volatile struct stm32f2_flash_regs *flash_regs;
flash_regs = (struct stm32f2_flash_regs *)STM32F2_FLASH_BASE;
if (wait_states > STM32F2_FLASH_ACR_LAT_MSK)
wait_states = STM32F2_FLASH_ACR_LAT_MSK;
flash_regs->acr = STM32F2_FLASH_ACR_PRFTEN |
STM32F2_FLASH_ACR_ICEN |
(wait_states << STM32F2_FLASH_ACR_LAT_BIT);
}
/*
* Initialize internal Flash interface
*/
......
......@@ -53,8 +53,6 @@ void reset_timer(void)
/*
* TBD
*/
return 0;
}
/*
......@@ -65,8 +63,6 @@ void __udelay(unsigned long usec)
/*
* TBD
*/
return 0;
}
/*
......
......@@ -29,6 +29,7 @@ COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
COBJS-$(CONFIG_STM32F2_GPIO) += stm32f2_gpio.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
......
......@@ -76,6 +76,7 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
COBJS-$(CONFIG_CORE10100) += core10100.o
COBJS-$(CONFIG_STM32F2_ETH) += stm32f2_eth.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
......
This diff is collapsed.
......@@ -52,6 +52,7 @@ COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_STM32F2_USART_CONSOLE) += stm32f2_usart.o
COBJS-$(CONFIG_USB_TTY) += usbtty.o
COBJS := $(sort $(COBJS-y))
......
......@@ -100,9 +100,9 @@
#define CONFIG_MEM_NVM_LEN (1024 * 1024)
#define CONFIG_MEM_RAM_BASE 0x20000000
#define CONFIG_MEM_RAM_LEN (16 * 1024)
#define CONFIG_MEM_RAM_LEN (32 * 1024)
#define CONFIG_MEM_RAM_BUF_LEN (32 * 1024)
#define CONFIG_MEM_MALLOC_LEN (12 * 1024)
#define CONFIG_MEM_MALLOC_LEN (60 * 1024)
#define CONFIG_MEM_STACK_LEN (4 * 1024)
/*
......@@ -126,7 +126,7 @@
* Store env in memory only
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_SIZE (4 * 1024)
/*
* Serial console configuration
......@@ -141,6 +141,21 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Ethernet configuration
*/
#define CONFIG_NET_MULTI
#define CONFIG_STM32F2_ETH
/*
* Ethernet RX buffers are malloced from the internal SRAM (more precisely,
* from CONFIG_SYS_MALLOC_LEN part of it). Each RX buffer has size of 1536B.
* So, keep this in mind when changing the value of the following config,
* which determines the number of ethernet RX buffers (number of frames which
* may be received without processing until overflow happens).
*/
#define CONFIG_SYS_RX_ETH_BUFFER 4
/*
* Console I/O buffer size
*/
......@@ -187,7 +202,7 @@
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#define CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
......@@ -216,7 +231,8 @@
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=60000000\0" \
/* FIXME: load to external RAM */ \
"loadaddr=0x20008000\0" \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
"ethaddr=C0:B1:3C:88:88:88\0" \
"ipaddr=172.17.4.206\0" \
......
......@@ -86,6 +86,7 @@ int uli526x_initialize(bd_t *bis);
int sh_eth_initialize(bd_t *bis);
int dm9000_initialize(bd_t *bis);
int core_eth_init(bd_t *bis);
int stm32f2_eth_init(bd_t *bis);
/* Boards with PCI network controllers can call this from their board_eth_init()
* function to initialize whatever's on board.
......
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