RT 64671: Port the current s/w functionality to A2F-LNX-EVB 2A

board/emcraft/a2f-lnx-evb/board.c

@@ -32,17 +32,41 @@ int board_init(void)
 	return 0;
 }
 
+int checkboard(void)
+{
+	printf("Board: A2F-LNX-EVB Rev %s, www.emcraft.com\n",
+		CONFIG_SYS_BOARD_REV_STR);
+	return 0;
+}
+
 int dram_init (void)
 {
 #if ( CONFIG_NR_DRAM_BANKS > 0 )
+	/*
+	 * External memory controller MUX configuration
+	 * The EMC _SEL bit in the EMC_MUX_CR register is used
+	 * to select either FPGA I/O or EMC I/O.
+	 * 1 -> The multiplexed I/Os are allocated to the EMC.
+	 */
+        A2F_SYSREG->emc_mux_cr = CONFIG_SYS_EMCMUXCR;
+
 	/*
 	 * EMC timing parameters for chip select 0
+	 * where the external SRAM memory resides on A2F-LNX-EVB.
 	 */
         A2F_SYSREG->emc_cs_0_cr = CONFIG_SYS_EMC0CS0CR;
 
+	/*
+	 * Fill in global info with description of SRAM configuration.
+	 */
+        gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
+        gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
 
-        gd->bd->bi_dram[0].start = EXT_RAM_BASE;
-        gd->bd->bi_dram[0].size = EXT_RAM_SIZE;
+	/*
+	 * EMC timing parameters for chip select 1
+	 * where the external Flash memory resides on A2F-LNX-EVB.
+	 */
+        A2F_SYSREG->emc_cs_1_cr = CONFIG_SYS_EMC0CS1CR;
 #endif
 
         return 0;

cpu/arm_cortexm3/cpu.c

@@ -33,15 +33,6 @@ int arch_cpu_init(void)
  	 */
 	my_uart_init(115200);
 
-	/*
-	 * External memory controller MUX configuration
-	 * The EMC _SEL bit in the EMC_MUX_CR register is used
-	 * to select either FPGA I/O or EMC I/O.
-	 * 1 -> The multiplexed I/Os are allocated to the EMC.
-	 */
-        A2F_SYSREG->emc_mux_cr = CONFIG_SYS_EMCMUXCR;
-        A2F_SYSREG->emc_cs_1_cr = CONFIG_SYS_EMC0CS1CR;
-
 	nvm_init();
 
 	timer_init();
@@ -54,20 +45,16 @@ int arch_cpu_init(void)
 	/*
 	 * Address of the kernel boot parameters.
 	 * Use start of the external RAM for that;
-	 * kernel resides at offset 0x8000.
+	 * kernel resides at offset 0x8000 in the external RAM.
 	 */
-	gd->bd->bi_boot_params = EXT_RAM_BASE;
+	gd->bd->bi_boot_params = CONFIG_SYS_RAM_BASE;
 
         return 0;
 }
 
 int print_cpuinfo(void)
 {
-        return 0;
-}
-
-int checkboard(void)
-{
+	printf("CPU: %s\n", "SmartFusion FPGA (Cortex-M3 Hard IP)");
         return 0;
 }
 

drivers/net/core10100.c

@@ -621,7 +621,7 @@ int core_eth_init(bd_t *bd)
 	netdev->iobase = (u32)MAC_BASE;
 	bp->base = (char *)MAC_BASE;
 
-	sprintf(netdev->name, "MAC0");
+	sprintf(netdev->name, "Core10/100");
 	netdev->init = core_init;
 
 	netdev->halt = core_halt;

drivers/serial/ns16550.c

@@ -22,7 +22,7 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
  * TO-DO: figure out the initialization procedure. 
  */
 
-#ifndef CONFIG_ARMCORTEXM3
+#ifndef CONFIG_SYS_ARMCORTEXM3
 	com_port->ier = 0x00;
 #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
 	com_port->mdr1 = 0x7;	/* mode select reset TL16C750*/
@@ -45,7 +45,7 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 #endif
 #endif /* CONFIG_OMAP */
 
-#endif /* CONFIG_ARMCORTEXM3 */
+#endif /* CONFIG_SYS_ARMCORTEXM3 */
 }
 
 #ifndef CONFIG_NS16550_MIN_FUNCTIONS

include/configs/a2f-lnx-evb.h

@@ -25,23 +25,30 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+/*
+ * Enable/disable debug messages
+ */
+#define DEBUG
+#undef DEBUG
+
 /*
  * This is an ARM Cortex-M3 CPU core
  */
-#define CONFIG_ARMCORTEXM3
+#define CONFIG_SYS_ARMCORTEXM3
+
 /*
  * This is the Actel SmartFusion (aka A2F) device
  */
-#define CONFIG_A2F
-
-/* System frequency (FCLK) coming out of reset */
-#define CONFIG_SYS_RESET_SYSCLCK_FREQ	80000000uL
+#define CONFIG_SYS_A2F
 
 /*
- * Enable/disable debug messages
+ * This is a specific revision of the board
  */
-#define DEBUG
-#undef DEBUG
+#define CONFIG_SYS_BOARD_REV		0x1A
+
+#if (CONFIG_SYS_BOARD_REV!=0x1A && CONFIG_SYS_BOARD_REV!=0x2A)
+#error CONFIG_SYS_BOARD_REV must be 1A or 2A
+#endif
 
 /*
  * Display CPU and Board information
@@ -49,64 +56,68 @@
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
 
-/* 
- * Enbale all those monitor commands that are really needed
- */
-
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_BOOTD
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_ECHO
-#undef CONFIG_CMD_EDITENV
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_ITEST
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG 
+#if (CONFIG_SYS_BOARD_REV==0x1A)
+# define CONFIG_SYS_BOARD_REV_STR	"1.A"
+#else
+# define CONFIG_SYS_BOARD_REV_STR	"2.A"
+#endif
 
-/* 
- * TO-DO: review this list
+/*
+ * Monitor prompt
  */
+#define CONFIG_SYS_PROMPT		"A2F-LNX-EVB> "
 
 /*
- * Configuration of the external RAM.
+ * We want to call the CPU specific initialization
  */
-#define CONFIG_NR_DRAM_BANKS        1
-#define EXT_RAM_BASE                0x70000000
-#define EXT_RAM_SIZE                (8 * 1024 * 1024)
-#define CONFIG_SYS_FLASH_BANK1_BASE 0x74000000
-//#define CONFIG_SYS_FLASH_BANK2_BASE 0x74800000
+#define CONFIG_ARCH_CPU_INIT
 
-/* External Memory Controller settings
- *
+/*
+ * System frequency (FCLK) coming out from reset
  */
+#define CONFIG_SYS_RESET_SYSCLCK_FREQ	80000000uL
 
-/* #define CONFIG_SYS_EMC0CS0CR	0x00002aad */ /* Slow timing */
-#define CONFIG_SYS_EMC0CS0CR	0x00002225
-#define CONFIG_SYS_EMC0CS1CR	0x000000af
+/*
+ * No interrupts
+ */
+#undef CONFIG_USE_IRQ
 
-#define CONFIG_SYS_EMCMUXCR		0x00000001
+/*
+ * Configuration of the external memory.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_RAM_BASE		0x70000000
+#if (CONFIG_SYS_BOARD_REV==0x1A)
+# define CONFIG_SYS_RAM_SIZE		(8 * 1024 * 1024)
+#else
+# define CONFIG_SYS_RAM_SIZE		(16 * 1024 * 1024)
+#endif
+#define CONFIG_SYS_FLASH_BANK1_BASE	0x74000000
 
 /*
- * MALLOC_LEN can't be more than the specified size!
- * Refer to u-boot.lds for further details.
+ * External Memory Controller settings
+ * Slow, safe timings for external SRAM
+#define CONFIG_SYS_EMC0CS0CR		0x00002aad
  */
-#define CONFIG_SYS_MALLOC_LEN	(1024*8)
 
 /*
- * We want to call the CPU specific initialization
+ * Optimized timings for external SRAM
  */
-#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_EMC0CS0CR		0x00002225
+/*
+ * Timings for external Flash
+ */
+#define CONFIG_SYS_EMC0CS1CR		0x000000af
+/*
+ * Settings for the EMC MUX register
+ */
+#define CONFIG_SYS_EMCMUXCR		0x00000001
 
 /*
- * No interrupts
+ * MALLOC_LEN can't be more than the specified size!
+ * Refer to u-boot.lds for further details.
  */
-#undef CONFIG_USE_IRQ
+#define CONFIG_SYS_MALLOC_LEN		(1024*8)
 
 /*
  * TO-DO: what is this? ... something to do with clocks...
@@ -118,11 +129,6 @@
  */
 #undef CONFIG_SYS_LONGHELP
 
-/*
- * Monitor prompt
- */
-#define CONFIG_SYS_PROMPT		"A2F-LNX-EVB> "
-
 /*
  * Console I/O buffer size
  */
@@ -191,12 +197,12 @@
 #define CONFIG_FLASH_CFI_DRIVER		1	/* Use the common driver */
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BANK1_BASE }
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max nmbr of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max nmbr of sctrs in chip */
 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
 
-#define CONFIG_SYS_MONITOR_BASE  0x0 
-#define CONFIG_MONITOR_IS_IN_RAM 1
+#define CONFIG_SYS_MONITOR_BASE  	0x0 
+#define CONFIG_MONITOR_IS_IN_RAM 	1
 
 /* ENV settings */
 #define CONFIG_ENV_IS_IN_FLASH 1
@@ -256,4 +262,24 @@
 #define MIIDELAY		udelay(1)
 #endif
 
+/* 
+ * Enable all those monitor commands that are needed
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_ECHO
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG 
+
+
 #endif /* __CONFIG_H */