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Commit a5a8b975 authored by Yuri Tikhonov's avatar Yuri Tikhonov
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RT72064. cortexm3: fix trailig whitespaces in cortexm3 related code 


Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
parent 72e57f02
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board/actel/a2f-actel-dev-brd/board.c
View file @ a5a8b975
......@@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
* FPGA Fabric may include the PSRAM_IP block, which is used to
* control the signals on the EMC interface to get access to
* the configuration registers of the external PSRAM, which
* allows to put the PSRAM into the faster Page Mode.
* allows to put the PSRAM into the faster Page Mode.
* The following data structure and the macros provide access
* to the control registers of PSRAM_IP.
* Note: PSRAM_IP may be accessed only when the EMC interface is
......@@ -67,14 +67,14 @@ void psram_page_mode(void)
unsigned int v;
/*
* Check if the PSRAM_IP IP block is there in the FPGA fabric.
*/
* Check if the PSRAM_IP IP block is there in the FPGA fabric.
*/
if (PSRAM_IP->magic == PSRAM_IP_MAGIC) {
/*
* Switch the EMC signals into FPGA mode.
*/
A2F_SYSREG->emc_mux_cr &= ~CONFIG_SYS_EMCMUXCR;
A2F_SYSREG->emc_mux_cr &= ~CONFIG_SYS_EMCMUXCR;
/*
* If so, perform the sequence to put PSRAM into Page Mode.
......@@ -95,19 +95,19 @@ void psram_page_mode(void)
v = PSRAM_IP->data_out;
/*
* If PSRAM has been successfully put into Page Mode,
* remember this in a software flag.
*/
* If PSRAM has been successfully put into Page Mode,
* remember this in a software flag.
*/
if (v == 0x90) {
psram_in_page_mode = 1;
}
}
/*
* Release the EMC from reset. It may have been put
* into reset by a design that installs the IP core
* for setting the external PSRAM into Page Mode.
*/
* Release the EMC from reset. It may have been put
* into reset by a design that installs the IP core
* for setting the external PSRAM into Page Mode.
*/
A2F_SYSREG->soft_rst_cr &= ~(1<<3);
/*
......
board/emcraft/a2f-lnx-evb/board.c
View file @ a5a8b975
......@@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
* FPGA Fabric may include the PSRAM_IP block, which is used to
* control the signals on the EMC interface to get access to
* the configuration registers of the external PSRAM, which
* allows to put the PSRAM into the faster Page Mode.
* allows to put the PSRAM into the faster Page Mode.
* The following data structure and the macros provide access
* to the control registers of PSRAM_IP.
* Note: PSRAM_IP may be accessed only when the EMC interface is
......@@ -67,14 +67,14 @@ void psram_page_mode(void)
unsigned int v;
/*
* Check if the PSRAM_IP IP block is there in the FPGA fabric.
*/
* Check if the PSRAM_IP IP block is there in the FPGA fabric.
*/
if (PSRAM_IP->magic == PSRAM_IP_MAGIC) {
/*
* Switch the EMC signals into FPGA mode.
*/
A2F_SYSREG->emc_mux_cr &= ~CONFIG_SYS_EMCMUXCR;
A2F_SYSREG->emc_mux_cr &= ~CONFIG_SYS_EMCMUXCR;
/*
* If so, perform the sequence to put PSRAM into Page Mode.
......@@ -95,19 +95,19 @@ void psram_page_mode(void)
v = PSRAM_IP->data_out;
/*
* If PSRAM has been successfully put into Page Mode,
* remember this in a software flag.
*/
* If PSRAM has been successfully put into Page Mode,
* remember this in a software flag.
*/
if (v == 0x90) {
psram_in_page_mode = 1;
}
}
/*
* Release the EMC from reset. It may have been put
* into reset by a design that installs the IP core
* for setting the external PSRAM into Page Mode.
*/
* Release the EMC from reset. It may have been put
* into reset by a design that installs the IP core
* for setting the external PSRAM into Page Mode.
*/
A2F_SYSREG->soft_rst_cr &= ~(1<<3);
/*
......
board/hoermann/a2f-hoermann-brd/board.c
View file @ a5a8b975
......@@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
* FPGA Fabric may include the PSRAM_IP block, which is used to
* control the signals on the EMC interface to get access to
* the configuration registers of the external PSRAM, which
* allows to put the PSRAM into the faster Page Mode.
* allows to put the PSRAM into the faster Page Mode.
* The following data structure and the macros provide access
* to the control registers of PSRAM_IP.
* Note: PSRAM_IP may be accessed only when the EMC interface is
......@@ -67,14 +67,14 @@ void psram_page_mode(void)
unsigned int v;
/*
* Check if the PSRAM_IP IP block is there in the FPGA fabric.
*/
* Check if the PSRAM_IP IP block is there in the FPGA fabric.
*/
if (PSRAM_IP->magic == PSRAM_IP_MAGIC) {
/*
* Switch the EMC signals into FPGA mode.
*/
A2F_SYSREG->emc_mux_cr &= ~CONFIG_SYS_EMCMUXCR;
A2F_SYSREG->emc_mux_cr &= ~CONFIG_SYS_EMCMUXCR;
/*
* If so, perform the sequence to put PSRAM into Page Mode.
......@@ -95,19 +95,19 @@ void psram_page_mode(void)
v = PSRAM_IP->data_out;
/*
* If PSRAM has been successfully put into Page Mode,
* remember this in a software flag.
*/
* If PSRAM has been successfully put into Page Mode,
* remember this in a software flag.
*/
if (v == 0x90) {
psram_in_page_mode = 1;
}
}
/*
* Release the EMC from reset. It may have been put
* into reset by a design that installs the IP core
* for setting the external PSRAM into Page Mode.
*/
* Release the EMC from reset. It may have been put
* into reset by a design that installs the IP core
* for setting the external PSRAM into Page Mode.
*/
A2F_SYSREG->soft_rst_cr &= ~(1<<3);
/*
......
cpu/arm_cortexm3/cmd_cptf.c
View file @ a5a8b975
......@@ -34,31 +34,31 @@ extern char _mem_ram_buf_base, _mem_ram_buf_size;
* which itself runs from the eNVM.
*/
static int __attribute__((section(".ramcode")))
__attribute__ ((long_call))
__attribute__ ((long_call))
envm_write_and_reset(ulong dst, ulong src, ulong size, int do_reset)
{
int ret = 0;
/*
* Copy the buffer to the destination.
*/
* Copy the buffer to the destination.
*/
if (envm_write((uint) dst, (void *) src, (uint) size) != size) {
ret = -1;
goto Done;
}
/*
* If the user needs a reset, do the reset
*/
* If the user needs a reset, do the reset
*/
if (do_reset) {
/*
* Cortex-M3 core reset.
*/
* Cortex-M3 core reset.
*/
reset_cpu(0);
/*
* Should never be here.
*/
* Should never be here.
*/
}
Done:
......@@ -86,8 +86,8 @@ int do_cptf(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
/*
* Parse the command arguments
*/
* Parse the command arguments
*/
dst = simple_strtoul(argv[1], NULL, 16);
if (argc >= 3) {
src = simple_strtoul(argv[2], NULL, 16);
......@@ -102,8 +102,8 @@ int do_cptf(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("%s: Updating eNVM. Please wait ...\n", (char *) argv[0]);
/*
* Copy the buffer to the destination.
*/
* Copy the buffer to the destination.
*/
if (envm_write_and_reset(dst, src, size, do_reset)) {
printf("%s: nvm_write_and_reset failed\n", (char *) argv[0]);
goto Done;
......
cpu/arm_cortexm3/start.c
View file @ a5a8b975
......@@ -58,7 +58,7 @@ static inline void __attribute__((used)) __disable_irq(void)
/*
* Exception-processing vectors:
*/
*/
unsigned int vectors[] __attribute__((section(".vectors"))) = {
/*
......@@ -67,23 +67,23 @@ unsigned int vectors[] __attribute__((section(".vectors"))) = {
*/
[0] = (unsigned long)&_mem_stack_end,
/*
/*
* Reset entry point
*/
*/
[1] = (unsigned int)&_start,
/*
* Other exceptions
*/
*/
[2 ... 165] = (unsigned int)&default_isr
};
/*
/*
* Reset entry point
*/
*/
void _start(void)
{
/*
/*
* Depending on the config parameter, enable or disable the WDT.
*/
#if !defined(CONFIG_HW_WATCHDOG)
......@@ -100,7 +100,7 @@ void _start(void)
/*
* Copy data and initialize BSS
* This is in lieu of the U-boot "conventional" relocation
* of code & data from Flash to RAM.
* of code & data from Flash to RAM.
* With Cortex-M3, we execute from NVRAM (internal Flash),
* having relocated data to internal RAM (and having cleared the BSS
* area in internal RAM as well)
......@@ -111,17 +111,17 @@ void _start(void)
memset(&_bss_start, 0, &_bss_end - &_bss_start);
/*
* In U-boot (armboot) lingvo, "go to the C code" -
* In U-boot (armboot) lingvo, "go to the C code" -
* in fact, with M3, we are at the C code from the very beginning.
* In actuality, this is the jump to the ARM generic start code.
* ...
* Note initialization of _armboot_start below. The ARM generic
* code expects that this variable is set to the upper boundary of
* the malloc pool area.
* the malloc pool area.
* For Cortex-M3, where we do not relocate the code to RAM, I set
* the malloc pool right behind the stack. See how armboot_start
* is defined in the CPU specific .lds file.
*/
*/
_armboot_start = (unsigned long)&_mem_stack_base;
start_armboot();
}
......@@ -133,7 +133,7 @@ void _start(void)
void __attribute__((naked, noreturn)) default_isr(void);
void default_isr(void)
{
/*
/*
* Dump the registers
*/
asm("mov r0, sp; bl dump_ctx");
......@@ -145,7 +145,7 @@ void default_isr(void)
/*
* Dump the registers on an exception we don't know how to process.
*/
*/
static void __attribute__((used)) dump_ctx(unsigned int *ctx)
{
static char *regs[] = {
......
include/configs/a2f-actel-dev-brd.h
View file @ a5a8b975
......@@ -147,7 +147,7 @@
# define CONFIG_SYS_EMC0CS1CR 0x0001B13F
#endif
/*
/*
* Settings for the CFI Flash driver
*/
#if (CONFIG_SYS_BOARD_REV==0x33)
......@@ -163,7 +163,7 @@
# define CONFIG_SYS_FLASH_PROTECTION 1
#endif
/*
/*
* U-boot environment configruation
*/
#define CONFIG_ENV_IS_IN_FLASH 1
......@@ -202,7 +202,7 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/*
/*
* Ethernet driver configuration
*/
#define CONFIG_NET_MULTI
......@@ -219,24 +219,24 @@
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_RAM_BASE + \
CONFIG_SYS_RAM_SIZE)
/*
/*
* Needed by "loadb"
*/
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_RAM_BASE
/*
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
*/
#define CONFIG_SYS_MONITOR_BASE 0x0
#define CONFIG_SYS_MONITOR_BASE 0x0
/*
* Monitor is not in flash. Needs to define this to prevent
* Monitor is not in flash. Needs to define this to prevent
* U-Boot from running flash_protect() on the monitor code.
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
#define CONFIG_MONITOR_IS_IN_RAM 1
/*
/*
* Enable all those monitor commands that are needed
*/
#include <config_cmd_default.h>
......@@ -275,7 +275,7 @@
"console=ttyS0,115200 panic=10"
#define CONFIG_BOOTCOMMAND "run flashboot"
/*
/*
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
......
include/configs/a2f-hoermann-brd.h
View file @ a5a8b975
......@@ -142,7 +142,7 @@
*/
#define CONFIG_SYS_EMC0CS1CR 0x00011137
/*
/*
* Settings for the CFI Flash driver
*/
#define CONFIG_SYS_FLASH_CFI 1
......@@ -154,7 +154,7 @@
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
#define CONFIG_SYS_FLASH_PROTECTION 1
/*
/*
* U-boot environment configruation
*/
#define CONFIG_ENV_IS_IN_FLASH 1
......@@ -187,7 +187,7 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/*
/*
* Ethernet driver configuration
*/
#define CONFIG_NET_MULTI
......@@ -204,24 +204,24 @@
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_RAM_BASE + \
CONFIG_SYS_RAM_SIZE)
/*
/*
* Needed by "loadb"
*/
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_RAM_BASE
/*
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
*/
#define CONFIG_SYS_MONITOR_BASE 0x0
#define CONFIG_SYS_MONITOR_BASE 0x0
/*
* Monitor is not in flash. Needs to define this to prevent
* Monitor is not in flash. Needs to define this to prevent
* U-Boot from running flash_protect() on the monitor code.
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
#define CONFIG_MONITOR_IS_IN_RAM 1
/*
/*
* Enable all those monitor commands that are needed
*/
#include <config_cmd_default.h>
......@@ -260,7 +260,7 @@
"console=ttyS0,115200 panic=10"
#define CONFIG_BOOTCOMMAND "run flashboot"
/*
/*
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
......
include/configs/a2f-lnx-evb.h
View file @ a5a8b975
......@@ -144,7 +144,7 @@
*/
#define CONFIG_SYS_EMC0CS1CR 0x00011137
/*
/*
* Settings for the CFI Flash driver
*/
#define CONFIG_SYS_FLASH_CFI 1
......@@ -155,7 +155,7 @@
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
/*
/*
* U-boot environment configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
......@@ -188,7 +188,7 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/*
/*
* Ethernet driver configuration
*/
#define CONFIG_NET_MULTI
......@@ -205,24 +205,24 @@
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_RAM_BASE + \
CONFIG_SYS_RAM_SIZE)
/*
/*
* Needed by "loadb"
*/
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_RAM_BASE
/*
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
*/
#define CONFIG_SYS_MONITOR_BASE 0x0
#define CONFIG_SYS_MONITOR_BASE 0x0
/*
* Monitor is not in flash. Needs to define this to prevent
* Monitor is not in flash. Needs to define this to prevent
* U-Boot from running flash_protect() on the monitor code.
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
#define CONFIG_MONITOR_IS_IN_RAM 1
/*
/*
* Enable all those monitor commands that are needed
*/
#include <config_cmd_default.h>
......@@ -261,7 +261,7 @@
"console=ttyS0,115200 panic=10"
#define CONFIG_BOOTCOMMAND "run flashboot"
/*
/*
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
......
include/configs/stm3220g-eval.h
View file @ a5a8b975
......@@ -150,13 +150,13 @@
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
*/
#define CONFIG_SYS_MONITOR_BASE 0x0
#define CONFIG_SYS_MONITOR_BASE 0x0
/*
* Monitor is not in flash. Needs to define this to prevent
* U-Boot from running flash_protect() on the monitor code.
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
#define CONFIG_MONITOR_IS_IN_RAM 1
/*
* Enable all those monitor commands that are needed
......
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