Commit ac2240f6 authored by Vladimir Khusainov's avatar Vladimir Khusainov

RT106081: Port U-Boot and uClinux to STM32F7

Initial skeleton of the STM32F7 SOM port. The configuration builds
but hasn't been yet tried on the target.
parent b324746b
......@@ -3245,6 +3245,9 @@ stm-som-1a_config : unconfig
}
@$(MKCONFIG) -a stm-som arm arm_cortexm3 stm-som emcraft stm32
stm32f7-som_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 stm32f7-som emcraft stm32
stm32f429-discovery_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 stm32f429-discovery \
stm stm32
......
#
# (C) Copyright 2011-2015
#
# Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
# Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := board.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
This diff is collapsed.
/*
* (C) Copyright 2011-2015
*
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
* Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Configuration settings for the Emcraft STM32F7 SOM
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#if !defined(CONFIG_SYS_BOARD_REV)
#define CONFIG_SYS_BOARD_REV 0x1A
#endif
/*
* Disable debug messages
*/
#undef DEBUG
/*
* This is an ARM Cortex-M7 CPU core.
* Also use the common Cortex-M3 and Cortex-M4 code.
*/
#define CONFIG_SYS_ARMCORTEXM3
#define CONFIG_SYS_ARMCORTEXM4
#define CONFIG_SYS_ARMCORTEXM7
/*
* This is an STM32 and STM32F7 device.
*/
#define CONFIG_SYS_STM32
#define CONFIG_SYS_STM32F7
/*
* Enable GPIO driver
*/
#define CONFIG_STM32F2_GPIO
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#if CONFIG_SYS_BOARD_REV == 0x1A
# define CONFIG_SYS_BOARD_REV_STR "1.A"
#else
# error "wrong board revision"
#endif
/*
* Monitor prompt
*/
#if CONFIG_SYS_BOARD_REV == 0x1A
# define CONFIG_SYS_PROMPT "STM32F7-SOM> "
#endif
/*
* We want to call the CPU specific initialization
*/
#define CONFIG_ARCH_CPU_INIT
/*
* Clock configuration (see mach-stm32/clock.c for details):
* - use PLL as the system clock;
* - use HSE as the PLL source;
* - configure PLL to get 168MHz system clock.
*/
#define CONFIG_STM32_SYS_CLK_PLL
#define CONFIG_STM32_PLL_SRC_HSE
#define CONFIG_STM32_HSE_HZ 12000000 /* 12 MHz */
#define CONFIG_STM32_PLL_M 12
#define CONFIG_STM32_PLL_N 336
#define CONFIG_STM32_PLL_P 2
#define CONFIG_STM32_PLL_Q 7
/*
* Number of clock ticks in 1 sec
*/
#define CONFIG_SYS_HZ 1000
/*
* Enable/disable h/w watchdog
*/
#undef CONFIG_HW_WATCHDOG
/*
* No interrupts
*/
#undef CONFIG_USE_IRQ
/*
* Memory layout configuration
*/
#define CONFIG_MEM_NVM_BASE 0x00000000
#define CONFIG_MEM_NVM_LEN (1024 * 1024 * 1)
#define CONFIG_ENVM 1
#if defined(CONFIG_ENVM)
# define CONFIG_SYS_ENVM_BASE 0x08000000
# define CONFIG_SYS_ENVM_LEN CONFIG_MEM_NVM_LEN
#endif
#define CONFIG_MEM_RAM_BASE 0x20000000
#define CONFIG_MEM_RAM_LEN (20 * 1024)
#define CONFIG_MEM_RAM_BUF_LEN (88 * 1024)
#define CONFIG_MEM_MALLOC_LEN (16 * 1024)
#define CONFIG_MEM_STACK_LEN (4 * 1024)
/*
* malloc() pool size
*/
#define CONFIG_SYS_MALLOC_LEN CONFIG_MEM_MALLOC_LEN
#define FSMC_NOR_PSRAM_CS_ADDR(n) (0x60000000 + ((n) - 1) * 0x4000000)
/*
* Configuration of the external SDRAM memory
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_SIZE (32 * 1024 * 1024)
#define CONFIG_SYS_RAM_CS 1
#define CONFIG_SYS_RAM_FREQ_DIV 2
#define CONFIG_SYS_RAM_BASE 0xC0000000
/*
* Configuration of the external Flash memory
*/
#define CONFIG_SYS_FLASH_CS 2
/*
* Flash is in ModeC, that means 'OE toggle on write'
*
* MBKEN(0) = 1, enable memory bank
* MTYP(3-2) = 0b10, NOR flash
* MWID(5-4) = 0b01, 16 bit
* FACCEN(6) = 1,
* reserved(7) = 0,
* WREN(12) = 1,
* EXTMOD(14) = 1
*/
#define CONFIG_SYS_FSMC_FLASH_BCR 0x00005059
/*
* Flash timinigs are almost same for write and read.
* See Spansion memory reference manual for S29GL128S10DHI010
* tACC(MAX) = ADDSET(3-0) = 110 ns = 18.48 HCLK (on 168 MHz)
* tRC(MIN) = DATAST(15-8) = 110 ns = 18.48 HCLK (on 168 MHz)
* tNE switch = BUSTURN(19-16) = 10 ns = 2 HCLK
* ACCMODE(29-28) = 0x2 (mode C)
*/
#define CONFIG_SYS_FSMC_FLASH_BTR 0x2002120f
#define CONFIG_SYS_FSMC_FLASH_BWTR 0x2002110f
#define CONFIG_FSMC_NOR_PSRAM_CS2_ENABLE
#define CONFIG_SYS_FLASH_BANK1_BASE \
FSMC_NOR_PSRAM_CS_ADDR(CONFIG_SYS_FLASH_CS)
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BANK1_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
#define CONFIG_SYS_FLASH_PROTECTION 1
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
/*
* Store env in Flash memory
*/
#if 0
# define CONFIG_ENV_IS_IN_ENVM
#else
# define CONFIG_ENV_IS_IN_FLASH
#endif
#define CONFIG_ENV_SIZE (4 * 1024)
#if defined(CONFIG_ENV_IS_IN_ENVM)
# define CONFIG_ENV_ADDR (CONFIG_SYS_ENVM_BASE + (128 * 1024))
#else
# define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BANK1_BASE
#endif
#define CONFIG_INFERNO 1
#define CONFIG_ENV_OVERWRITE 1
/*
* Serial console configuration
*/
#define CONFIG_STM32_USART_CONSOLE
/*
* USART1, TX PB.6, RX PA.10
*/
#define CONFIG_STM32_USART_PORT 1 /* USART1 */
#define CONFIG_STM32_USART_TX_IO_PORT 1 /* PORTB */
#define CONFIG_STM32_USART_TX_IO_PIN 6 /* GPIO6 */
#define CONFIG_STM32_USART_RX_IO_PORT 0 /* PORTA */
#define CONFIG_STM32_USART_RX_IO_PIN 10 /* GPIO10 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Ethernet configuration
*/
#define CONFIG_NET_MULTI
#define CONFIG_STM32_ETH
#define CONFIG_STM32_ETH_RMII
/*
* Ethernet RX buffers are malloced from the internal SRAM (more precisely,
* from CONFIG_SYS_MALLOC_LEN part of it). Each RX buffer has size of 1536B.
* So, keep this in mind when changing the value of the following config,
* which determines the number of ethernet RX buffers (number of frames which
* may be received without processing until overflow happens).
*/
#define CONFIG_SYS_RX_ETH_BUFFER 4
/*
* Console I/O buffer size
*/
#define CONFIG_SYS_CBSIZE 256
/*
* Print buffer size
*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_RAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_RAM_BASE + \
CONFIG_SYS_RAM_SIZE)
/*
* Needed by "loadb"
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_RAM_BASE
/*
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
*/
#define CONFIG_SYS_MONITOR_BASE 0x0
/*
* Monitor is not in flash. Needs to define this to prevent
* U-Boot from running flash_protect() on the monitor code.
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
/*
* Enable all those monitor commands that are needed
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BOOTD
#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_ECHO
#undef CONFIG_CMD_EDITENV
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_ITEST
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_MISC
#define CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
#if CONFIG_SYS_BOARD_REV == 0x1A
# undef CONFIG_CMD_BUFCOPY
#else
# define CONFIG_CMD_BUFCOPY
#endif
/*
* To save memory disable long help
*/
#undef CONFIG_SYS_LONGHELP
/*
* Max number of command args
*/
#define CONFIG_SYS_MAXARGS 16
/*
* Auto-boot sequence configuration
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTCOMMAND "run flashboot"
/* boot args and env */
#define CONFIG_HOSTNAME stm32f7-som
#define CONFIG_BOOTARGS "stm32_platform=stm32f7-som " \
"console=ttyS0,115200 panic=10"
#define LOADADDR "0xC0007FC0"
#define REV_EXTRA_ENV \
"envmboot=run addip;bootm ${envmaddr}\0" \
"envmupdate=tftp ${image};" \
"cptf ${envmaddr} ${loadaddr} ${filesize}\0" \
"flashboot=run addip;bootm ${flashaddr}\0" \
"update=tftp ${image};" \
"prot off ${flashaddr} +${filesize};" \
"era ${flashaddr} +${filesize};" \
"cp.b ${loadaddr} ${flashaddr} ${filesize};" \
"setenv kernelsize ${filesize};" \
"setenv filesize; setenv fileaddr;" \
"saveenv\0"
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=" LOADADDR "\0" \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
"flashaddr=64020000\0" \
"envmaddr=08040000\0" \
"ethaddr=C0:B1:3C:88:88:85\0" \
"ipaddr=172.17.4.206\0" \
"serverip=172.17.0.1\0" \
"image=stm32f4x9/uImage\0" \
"stdin=serial\0" \
"netboot=tftp ${image};run addip;bootm\0" \
REV_EXTRA_ENV
/*
* Linux kernel boot parameters configuration
*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#endif /* __CONFIG_H */
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