Commit ae1cc580 authored by Alexander Potashev's avatar Alexander Potashev
Browse files

RT76821. twr-k70f120m: configure the LCD contoller clock

 * Use the same PLL (PLL0 or PLL1) for the LCDC source clock as we use
for the MCGOUTCLK.
 * Set LCDC_DIV to 4, set LCDC_FRAC to 1. Given the PLL output rate is 120 MHz,
the LCDC clock rate will be 30 MHz.
parent cfe82b81
......@@ -362,6 +362,24 @@
#define KINETIS_SIM_SOPT2_NFC_CLKSEL_NFCDIV 0
/* EXTAL1 clock */
#define KINETIS_SIM_SOPT2_NFC_CLKSEL_EXTAL1 KINETIS_SIM_SOPT2_NFC_CLKSEL_MSK
/*
* LCD Controller source clock
*/
#define KINETIS_SIM_SOPT2_LCDCSRC_BITS 26
#define KINETIS_SIM_SOPT2_LCDCSRC_MSK (3 << KINETIS_SIM_SOPT2_LCDCSRC_BITS)
/* MCGPLL0CLK */
#define KINETIS_SIM_SOPT2_LCDCSRC_PLL0 (1 << KINETIS_SIM_SOPT2_LCDCSRC_BITS)
/* MCGPLL1CLK */
#define KINETIS_SIM_SOPT2_LCDCSRC_PLL1 (2 << KINETIS_SIM_SOPT2_LCDCSRC_BITS)
/*
* LCD Controller clock select
*/
#define KINETIS_SIM_SOPT2_LCDC_CLKSEL_MSK (1 << 14)
/* Clock divider LCDC pixel clock */
#define KINETIS_SIM_SOPT2_LCDC_CLKSEL_LCDCDIV 0
/* EXTAL1 clock */
#define KINETIS_SIM_SOPT2_LCDC_CLKSEL_EXTAL1 \
KINETIS_SIM_SOPT2_LCDC_CLKSEL_MSK
/*
* System Clock Divider Register 1
......@@ -375,6 +393,22 @@
/* Clock 4 output divider value (for the flash clock) */
#define KINETIS_SIM_CLKDIV1_OUTDIV4_BITS 16
/*
* System Clock Divider Register 3
*/
/* LCD Controller clock divider divisor */
#define KINETIS_SIM_CLKDIV3_LCDCDIV_BITS 16
#define KINETIS_SIM_CLKDIV3_LCDCDIV_BITWIDTH 12
#define KINETIS_SIM_CLKDIV3_LCDCDIV_MSK \
(((1 << KINETIS_SIM_CLKDIV3_LCDCDIV_BITWIDTH) - 1) << \
KINETIS_SIM_CLKDIV3_LCDCDIV_BITS)
/* LCD Controller clock divider fraction */
#define KINETIS_SIM_CLKDIV3_LCDCFRAC_BITS 8
#define KINETIS_SIM_CLKDIV3_LCDCFRAC_BITWIDTH 8
#define KINETIS_SIM_CLKDIV3_LCDCFRAC_MSK \
(((1 << KINETIS_SIM_CLKDIV3_LCDCFRAC_BITWIDTH) - 1) << \
KINETIS_SIM_CLKDIV3_LCDCFRAC_BITS)
/*
* System Clock Divider Register 4
*/
......@@ -396,8 +430,10 @@
*/
#ifdef KINETIS_MCGOUT_PLL1
#define KINETIS_SIM_SOPT2_NFCSRC KINETIS_SIM_SOPT2_NFCSRC_PLL1
#define KINETIS_SIM_SOPT2_LCDCSRC KINETIS_SIM_SOPT2_LCDCSRC_PLL1
#else
#define KINETIS_SIM_SOPT2_NFCSRC KINETIS_SIM_SOPT2_NFCSRC_PLL0
#define KINETIS_SIM_SOPT2_LCDCSRC KINETIS_SIM_SOPT2_LCDCSRC_PLL0
#endif /* KINETIS_MCGOUT_PLL1 */
/*
......@@ -698,6 +734,27 @@ static void clock_setup(void)
KINETIS_SIM_SOPT2_NFCSRC |
KINETIS_SIM_SOPT2_NFC_CLKSEL_NFCDIV;
#ifdef KINETIS_LCDCCLK_DIV
/*
* Configure the LCD Controller clock source
*/
KINETIS_SIM->sopt2 =
(KINETIS_SIM->sopt2 & ~(KINETIS_SIM_SOPT2_LCDCSRC_MSK |
KINETIS_SIM_SOPT2_LCDC_CLKSEL_MSK)) |
KINETIS_SIM_SOPT2_LCDCSRC |
KINETIS_SIM_SOPT2_LCDC_CLKSEL_LCDCDIV;
/*
* Configure the LCD Controller clock divider
*/
KINETIS_SIM->clkdiv3 =
(KINETIS_SIM->clkdiv3 & ~(KINETIS_SIM_CLKDIV3_LCDCDIV_MSK |
KINETIS_SIM_CLKDIV3_LCDCFRAC_MSK)) |
((KINETIS_LCDCCLK_DIV - 1) <<
KINETIS_SIM_CLKDIV3_LCDCDIV_BITS) |
((KINETIS_LCDCCLK_FRAC - 1) <<
KINETIS_SIM_CLKDIV3_LCDCFRAC_BITS);
#endif /* KINETIS_LCDCCLK_DIV */
/*
* TBD: Configure clock dividers for USB and I2S here
* via KINETIS_SIM->clkdiv2
......
......@@ -102,6 +102,10 @@
#define KINETIS_NFCCLK_DIV 5
/* NFC clock fraction: do no multiply */
#define KINETIS_NFCCLK_FRAC 1
/* LCDC clock divider: PLL/4 = 120/4 = 30 MHz */
#define KINETIS_LCDCCLK_DIV 4
/* LCDC clock fraction: do no multiply */
#define KINETIS_LCDCCLK_FRAC 1
/* PLL input divider: 50/5 = 10 MHz */
#define KINETIS_PLL_PRDIV 5
/* PLL multiplier: 10*24/2 = 120 MHz */
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment