RT76821. twr-k70f120m: configure the LCD contoller clock
* Use the same PLL (PLL0 or PLL1) for the LCDC source clock as we use for the MCGOUTCLK. * Set LCDC_DIV to 4, set LCDC_FRAC to 1. Given the PLL output rate is 120 MHz, the LCDC clock rate will be 30 MHz.
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