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Sami Nurmenniemi
u-boot-stm32
Commits
aec70c45
Commit
aec70c45
authored
Apr 08, 2013
by
Dmitry Konyshev
Browse files
RT #83884 Address review comments; minor corrections
parent
11275e33
Changes
7
Hide whitespace changes
Inline
Side-by-side
common/cmd_mem.c
View file @
aec70c45
...
...
@@ -454,12 +454,12 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#endif
#ifdef CONFIG_SPIFI
if
(
spifi_addr
(
dest
))
{
if
(
spifi_addr
(
addr
))
{
if
(
spifi_addr
(
dest
)
||
spifi_addr
(
dest
+
count
)
)
{
if
(
spifi_addr
(
addr
)
||
spifi_addr
(
addr
+
count
)
)
{
puts
(
"Cannot copy from SPIFI to SPIFI, aborting.
\n\r
"
);
return
1
;
}
if
(
!
spifi_addr
(
dest
+
count
))
{
if
(
!
spifi_addr
(
dest
)
||
!
spifi_addr
(
dest
+
count
))
{
puts
(
"Cannot copy across SPIFI boundaries, aborting.
\n\r
"
);
return
1
;
}
...
...
common/env_spifi.c
View file @
aec70c45
/* LowLevel function for SPIFI environment support
*
* (C) Copyright 201
2
* (C) Copyright 201
3
*
* Dmitry Konyshev, Emcraft Systems, probables@emcraft.com
*
...
...
@@ -25,6 +25,10 @@
#include
<environment.h>
#include
<linux/stddef.h>
#if defined(CONFIG_SPIFI)
#include
<spifi.h>
#endif
DECLARE_GLOBAL_DATA_PTR
;
env_t
*
env_ptr
=
NULL
;
...
...
cpu/arm_cortexm3/lpc18xx/Makefile
View file @
aec70c45
...
...
@@ -29,7 +29,10 @@ include $(TOPDIR)/config.mk
LIB
=
$(obj)
lib
$(SOC)
.a
COBJS
:=
clock.o cpu.o envm.o wdt.o spifi.o
COBJS
:=
clock.o cpu.o envm.o wdt.o
ifeq
($(CONFIG_SPIFI),y)
COBJS
+=
spifi.o
endif
SOBJS
:=
SRCS
:=
$(COBJS:.o=.c)
...
...
cpu/arm_cortexm3/lpc18xx/spifi.c
View file @
aec70c45
...
...
@@ -22,8 +22,6 @@
#include
<common.h>
#include
"spifilib/spifilib.h"
#if defined(CONFIG_SPIFI)
static
SPIFIobj
spifi_obj
;
const
spifilib_header_t
*
spifilib_ram_hdr
=
NULL
;
...
...
@@ -76,4 +74,3 @@ void spifi_cancel_mem_mode(void)
spifilib_ram_hdr
->
cancel_mem_mode_func
(
&
spifi_obj
);
}
#endif
cpu/arm_cortexm3/lpc18xx/spifilib/spifilib.c
View file @
aec70c45
...
...
@@ -23,7 +23,7 @@
int32_t
cancel_mem_mode
(
SPIFIobj
*
obj
);
const
spifilib_header_t
spilib_hdr
__attribute__
((
section
(
".rodata.spifilib.header"
)))
=
const
spifilib_header_t
spilib_hdr
__attribute__
((
section
(
".rodata.spifilib.header"
)))
=
{
SPIFILIB_SIG
,
(
spifilib_header_t
*
)
&
spilib_hdr
,
...
...
cpu/arm_cortexm3/lpc18xx/spifilib/spifilib.h
View file @
aec70c45
...
...
@@ -25,7 +25,9 @@
#include
"spifi_rom_api.h"
#define SPIFILIB_SIG 0x591F121B
#define SPIFILIB_SIZE 16*1024
#define SPIFILIB_SIZE (16*1024)
#define SPIFI_BASE_ADDR 0x14000000
typedef
int32_t
(
*
spifi_init_t
)(
SPIFIobj
*
obj
,
uint32_t
csHigh
,
uint32_t
options
,
uint32_t
mhz
);
typedef
int32_t
(
*
spifi_program_t
)(
SPIFIobj
*
obj
,
char
*
source
,
SPIFIopers
*
opers
);
...
...
@@ -43,6 +45,6 @@ typedef struct spifilib_header_s
spifi_cancel_mem_mode_t
cancel_mem_mode_func
;
}
spifilib_header_t
;
const
spifilib_header_t
*
spifilib_flash_hdr
=
(
spifilib_header_t
*
)(
0x14000000
+
112
*
1024
);
const
spifilib_header_t
*
spifilib_flash_hdr
=
(
spifilib_header_t
*
)(
SPIFI_BASE_ADDR
+
112
*
1024
);
#endif
include/configs/lpc4350-eval.h
View file @
aec70c45
...
...
@@ -146,13 +146,13 @@
*/
#define CONFIG_LPC18XX_EMC_HALFCPU
/* Uncomment the following line to disable Flash support */
/* #define CONFIG_SYS_NO_FLASH */
#ifndef CONFIG_SYS_NO_FLASH
/*
* Configuration of the external Flash memory
*/
/* Define this to enable NOR Flash support */
#define CONFIG_SYS_FLASH_CS 0
#if defined(CONFIG_SYS_FLASH_CS)
#define CONFIG_SYS_FLASH_CFG 0x81
/* 16 bit, Byte Lane enabled */
#define CONFIG_SYS_FLASH_WE (1 - 1)
/* Minimum is enough */
#define CONFIG_SYS_FLASH_OE 0
/* Minimum is enough */
...
...
@@ -171,20 +171,11 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BANK1_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#endif
/*
* Use the memory mapped QSPI Flash
*/
#define CONFIG_SPIFI
#define CONFIG_SPIFI_BASE 0x14000000
#define CONFIG_SPIFI_SIZE (16*1024*1024)
#define CONFIG_ENV_IS_IN_
SPIFI
#define CONFIG_ENV_IS_IN_
FLASH
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR \
(CONFIG_SPIFI_BASE + 128 * 1024)
#define CONFIG_INFERNO 1
(CONFIG_SYS_FLASH_BANK1_BASE + 128 * 1024)
#define CONFIG_ENV_OVERWRITE 1
/*
...
...
@@ -194,6 +185,50 @@
#define CONFIG_LPC18XX_NORFLASH_BOOTSTRAP_WORKAROUND
/* The image contents go immediately after the 16-byte header */
#define CONFIG_LPC18XX_NORFLASH_IMAGE_OFFSET 16
#endif
/* Uncomment the following line to enable the SPIFI interface */
/* #define CONFIG_SPIFI */
#ifdef CONFIG_SPIFI
#define CONFIG_SPIFI_BASE 0x14000000
#define CONFIG_SPIFI_SIZE (16*1024*1024)
#ifndef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_IS_IN_SPIFI
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR \
(CONFIG_SPIFI_BASE + 128 * 1024)
#define CONFIG_ENV_OVERWRITE 1
#endif
#endif
/* Uncomment the following line to enable SPI */
/* #define CONFIG_LPC_SPI */
#ifdef CONFIG_LPC_SPI
#ifdef CONFIG_SPIFI
#error SPI cannot be used along with SPIFI
#endif
#define CONFIG_LPC_SPI_PINS { \
{{0x3, 3}, LPC18XX_IOMUX_CONFIG(1, 0, 0, 1, 0, 0)}, \
{{0x3, 6}, LPC18XX_IOMUX_CONFIG(1, 0, 0, 1, 1, 1)}, \
{{0x3, 7}, LPC18XX_IOMUX_CONFIG(1, 0, 0, 1, 0, 0)}, \
{{0x3, 8}, LPC18XX_IOMUX_CONFIG(4, 0, 0, 1, 0, 0)} \
}
#define CONFIG_LPC_CS_GPIO {5, 11}
/*
* Configure SPI Flash
*/
#define CONFIG_SPI_FLASH 1
#define CONFIG_SPI_FLASH_SPANSION 1
#define CONFIG_SPI_FLASH_BUS 0
#define CONFIG_SPI_FLASH_CS 0
#define CONFIG_SPI_FLASH_MODE 0
#define CONFIG_SPI_FLASH_SPEED (clock_get(CLOCK_SPI) / 8)
#define CONFIG_SF_DEFAULT_SPEED CONFIG_SPI_FLASH_SPEED
#define CONFIG_SF_DEFAULT_MODE CONFIG_SPI_FLASH_MODE
#endif
/*
* Serial console configuration
...
...
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