Commit b79aa072 authored by Alexander Potashev's avatar Alexander Potashev
Browse files

RT77744. lpc4350-eval: NOR flash support

 * Reuse the code from EA-LPC1788's NOR flash support;
 * Improve NOR flash timings;
 * Place U-Boot environment at address 0x20000 (128 KBytes) in NOR
flash. We will store U-Boot image in the first 128 KBytes of NOR flash
when booting from NOR flash.
 * Place Linux kernel image at address 0x40000 (256 KBytes) in NOR
flash. We will store U-Boot image and U-Boot environment in the first
128 KBytes of NOR flash.
parent 791d3ebe
......@@ -404,6 +404,36 @@ static const struct lpc18xx_pin_config hitex_lpc4350_iomux[] = {
/* P2.9 = A0 - SDRAM */
{{0x2, 9}, LPC18XX_IOMUX_EMC_CONFIG(3)},
#endif /* CONFIG_NR_DRAM_BANKS */
#if defined(CONFIG_SYS_FLASH_CS)
/*
* Configuration for EMC pins used only for NOR flash
*/
/* P1.3 = OE# - NOR */
{{0x1, 3}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.4 = BLS0# - NOR */
{{0x1, 4}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P6.6 = BLS1# - NOR */
{{0x6, 6}, LPC18XX_IOMUX_EMC_CONFIG(1)},
/* P1.5 = CS0# - NOR */
{{0x1, 5}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P2.1 = A12 - NOR */
{{0x2, 1}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P6.7 = A15 - NOR */
{{0x6, 7}, LPC18XX_IOMUX_EMC_CONFIG(1)},
/* PD.15 = A17 - NOR */
{{0xD, 15}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PD.16 = A16 - NOR */
{{0xD, 16}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* PE.0 = A18 - NOR */
{{0xE, 0}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.1 = A19 - NOR */
{{0xE, 1}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.2 = A20 - NOR */
{{0xE, 2}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* PE.3 = A21 - NOR */
{{0xE, 3}, LPC18XX_IOMUX_EMC_CONFIG(3)},
#endif /* CONFIG_SYS_FLASH_CS */
};
/*
......@@ -423,6 +453,8 @@ static void iomux_init(void)
*/
int board_init(void)
{
volatile struct lpc_emc_st_regs *st;
/*
* Set SDRAM clock output delay to ~3.5ns (0x7777),
* the SDRAM chip does not work otherwise.
......@@ -442,6 +474,17 @@ int board_init(void)
*/
iomux_init();
#ifdef CONFIG_SYS_FLASH_CS
/* Set timing for flash */
st = &LPC_EMC->st[CONFIG_SYS_FLASH_CS];
st->cfg = CONFIG_SYS_FLASH_CFG;
st->we = CONFIG_SYS_FLASH_WE;
st->oe = CONFIG_SYS_FLASH_OE;
st->rd = CONFIG_SYS_FLASH_RD;
st->page = CONFIG_SYS_FLASH_PAGE;
st->wr = CONFIG_SYS_FLASH_WR;
st->ta = CONFIG_SYS_FLASH_TA;
#endif
return 0;
}
......@@ -579,3 +622,16 @@ int board_eth_init(bd_t *bis)
return lpc18xx_eth_driver_init(bis);
}
#endif
#ifdef CONFIG_FLASH_CFI_LEGACY
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI flash */
info->portwidth = FLASH_CFI_16BIT;
info->chipwidth = FLASH_CFI_BY16;
info->interface = FLASH_CFI_X16;
return 1;
} else
return 0;
}
#endif
......@@ -140,14 +140,47 @@
*/
#define CONFIG_LPC18XX_EMC_HALFCPU
/*
* Configuration of the external Flash memory
*/
/* Define this to enable NOR Flash support */
#define CONFIG_SYS_FLASH_CS 0
#if defined(CONFIG_SYS_FLASH_CS)
#define CONFIG_SYS_FLASH_CFG 0x81 /* 16 bit, Byte Lane enabled */
#define CONFIG_SYS_FLASH_WE (1 - 1) /* Minimum is enough */
#define CONFIG_SYS_FLASH_OE 0 /* Minimum is enough */
#define CONFIG_SYS_FLASH_RD (15 - 1) /* 70ns at 204MHz */
#define CONFIG_SYS_FLASH_PAGE (15 - 1) /* 70ns at 204MHz */
#define CONFIG_SYS_FLASH_WR 0x1f /* Maximum */
#define CONFIG_SYS_FLASH_TA 0x0f /* Maximum */
#define CONFIG_SYS_FLASH_BANK1_BASE 0x1C000000 /* CS0 */
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_FLASH_CFI_LEGACY 1
#define CONFIG_SYS_FLASH_LEGACY_2Mx16 1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BANK1_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 1024
/*
* Store env in flash.
*/
#define CONFIG_ENV_IS_IN_FLASH
#else
/*
* Store env in memory only, if no flash.
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#endif
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BANK1_BASE
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_FLASH_BANK1_BASE + 128 * 1024)
#define CONFIG_INFERNO 1
#define CONFIG_ENV_OVERWRITE 1
......@@ -288,7 +321,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x28000000\0" \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
"flashaddr=1C020000\0" \
"flashaddr=1C040000\0" \
"flashboot=run addip;bootm ${flashaddr}\0" \
"ethaddr=C0:B1:3C:88:88:90\0" \
"ipaddr=172.17.4.215\0" \
......
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