RT73025. ea-lpc1788: reuse ns16550 driver for serial console

Options that needs to be set in the board configuration file are
superfluous, because there is are no lpc178x-specific headers visible to
drivers/serial/serial.c where we could place extra (board-independent)
options.

Power for the UART will be enabled in the new function
`cortex_m3_soc_init()`.

cpu/arm_cortexm3/cpu.c

@@ -27,6 +27,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_ARMCORTEXM3_SOC_INIT)
+extern void cortex_m3_soc_init(void);
+#endif
+
 /*
  * CPU specific initilization
  */
@@ -60,6 +64,13 @@ int arch_cpu_init(void)
 # error "Unsupported Cortex-M3 SOC."
 #endif
 
+	/*
+	 * SoC configuration code that cannot be put into drivers
+	 */
+#if defined(CONFIG_ARMCORTEXM3_SOC_INIT)
+	cortex_m3_soc_init();
+#endif
+
 	/*
 	 * Address of the kernel boot parameters.
 	 * Use start of the external RAM for that;

cpu/arm_cortexm3/lpc178x/Makefile

@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	:= clock.o cpu.o envm.o wdt.o
+COBJS	:= clock.o cpu.o envm.o power.o soc.o wdt.o
 SOBJS	:=
 
 SRCS	:= $(COBJS:.o=.c)

cpu/arm_cortexm3/lpc178x/clock.c

@@ -202,75 +202,6 @@ static u32 clock_val[CLOCK_END];
 #define LPC178X_PLL_FEED_KEY1	0xAA
 #define LPC178X_PLL_FEED_KEY2	0x55
 
-/*
- * PLL register map
- * Used for PLL0 at 0x400FC080 and for PLL1 at 0x400FC0A0.
- */
-struct lpc178x_pll_regs {
-	u32 con;	/* PLL Control register */
-	u32 cfg;	/* PLL Configuration register */
-	u32 stat;	/* PLL Status register */
-	u32 feed;	/* PLL Feed register */
-};
-
-/*
- * SCC (System and Clock Control) register map
- * Should be mapped at 0x400FC000.
- */
-/*
- * TODO: convert to STM32/SmartFusion structure style,
- * i.e. use "rsvN[M]" hole fillers instead of "union"s for alignment.
- * (Not doing this until most lpc178x device drivers are implemented
- * and all necessary registers in this structure are known.)
- */
-struct lpc178x_scc_regs {
-	/* 0x400FC000: Flash Accelerator Configuration Register */
-	union {
-		u8 align0[0x80];
-	};
-
-	/* 0x400FC080: PLL0 registers */
-	union {
-		u8 align1[0x20];
-		struct lpc178x_pll_regs pll0; /* PLL0 registers */
-	};
-
-	/* 0x400FC0A0: PLL1 registers */
-	union {
-		u8 align2[0x20];
-		struct lpc178x_pll_regs pll1; /* PLL1 registers */
-	};
-
-	/* 0x400FC0C0: Power control registers */
-	union {
-		u8 align3[0x40];
-	};
-
-	/* 0x400FC100: Clock control */
-	union {
-		u8 align4[0xA0];
-		struct {
-			u32 emcclksel;	/* External Memory Controller
-						Clock Selection register */
-			u32 cclksel;	/* CPU Clock Selection register */
-			u32 usbclksel;	/* USB Clock Selection register */
-			u32 clksrcsel;	/* Clock Source Selection register */
-		};
-	};
-
-	/* 0x400FC1A0 */
-	u32 scs;	/* System Controls and Status register */
-	u32 rsv0;
-	u32 pclksel;	/* Peripheral Clock Selection register */
-};
-
-/*
- * SCC registers base
- */
-#define LPC178X_SCC_BASE		(LPC178X_APB1PERIPH_BASE + 0x0007C000)
-#define LPC178X_SCC			((volatile struct lpc178x_scc_regs *) \
-					LPC178X_SCC_BASE)
-
 /*
  * Apply changes made in PLLCON and PLLCFG
  *

drivers/serial/lpc178x_uart.c → cpu/arm_cortexm3/lpc178x/power.c

@@ -19,79 +19,17 @@
  * MA 02111-1307 USA
  */
 
-/*
- * EA-LPC178X UART driver
- */
-
 #include <common.h>
 
-/*
- * Initialize the serial port.
- */
-int serial_init(void)
-{
-	/*
-	 * TBD
-	 */
-
-	return 0;
-}
-
-/*
- * Set new baudrate.
- */
-void serial_setbrg(void)
-{
-	/*
-	 * TBD
-	 */
-
-	return;
-}
-
-/*
- * Read a single character from the serial port.
- */
-int serial_getc(void)
-{
-	/*
-	 * TBD
-	 */
-
-	return 0;
-}
-
-/*
- * Put a single character to the serial port.
- */
-void serial_putc(const char c)
-{
-	/*
-	 * TBD
-	 */
-
-	return;
-}
+#include <asm/arch/lpc178x.h>
 
 /*
- * Put a string ('\0'-terminated) to the serial port.
+ * Enable or disable power on a peripheral device (timers, UARTs, USB, etc)
  */
-void serial_puts(const char *s)
+void lpc178x_periph_enable(u32 pconp_mask, int enable)
 {
-	while (*s)
-		serial_putc(*s++);
+	if (enable)
+		LPC178X_SCC->pconp |= pconp_mask;
+	else
+		LPC178X_SCC->pconp &= ~pconp_mask;
 }
-
-/*
- * Test whether a character in in the RX buffer.
- */
-int serial_tstc(void)
-{
-	/*
-	 * TBD
-	 */
-
-	return 0;
-}
-
-

cpu/arm_cortexm3/lpc178x/soc.c

+/*
+ * (C) Copyright 2011
+ *
+ * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include "soc.h"
+
+/*
+ * UART will not work without running its power-on code in
+ * `cortex_m3_soc_init()`.
+ */
+#if defined(CONFIG_LPC178X_UART_PORT) && !defined(CONFIG_ARMCORTEXM3_SOC_INIT)
+#error UART enabled, but it requires CONFIG_ARMCORTEXM3_SOC_INIT
+#endif
+
+/*
+ * 1-bit masks for PCONP (Power Control for Peripherals register) for every
+ * UART that enable power on these UARTs
+ */
+#ifdef CONFIG_LPC178X_UART_PORT
+static const u32 uart_pconp_mask[] = {
+	LPC178X_SCC_PCONP_PCUART0_MSK, LPC178X_SCC_PCONP_PCUART1_MSK,
+	LPC178X_SCC_PCONP_PCUART2_MSK, LPC178X_SCC_PCONP_PCUART3_MSK,
+	LPC178X_SCC_PCONP_PCUART4_MSK
+};
+#endif
+
+/*
+ * SoC configuration code that cannot be put into drivers
+ */
+#ifdef CONFIG_ARMCORTEXM3_SOC_INIT
+void cortex_m3_soc_init(void)
+{
+#ifdef CONFIG_LPC178X_UART_PORT
+	/*
+	 * Enable power on the chosen UART
+	 */
+	lpc178x_periph_enable(uart_pconp_mask[CONFIG_LPC178X_UART_PORT], 1);
+#endif
+}
+#endif

cpu/arm_cortexm3/soc.h

+/*
+ * (C) Copyright 2011
+ * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ARM_CORTEXM3_SOC_H__
+#define __ARM_CORTEXM3_SOC_H__
+
+/*
+ * SoC initialization code that cannot be put into drivers.
+ */
+#ifdef CONFIG_ARMCORTEXM3_SOC_INIT
+extern void cortex_m3_soc_init(void);
+#endif
+
+#endif /* __ARM_CORTEXM3_SOC_H__ */

drivers/serial/Makefile

@@ -53,7 +53,6 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
 COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
 COBJS-$(CONFIG_STM32_USART_CONSOLE) += stm32_usart.o
-COBJS-$(CONFIG_LPC178X_UART_CONSOLE) += lpc178x_uart.o
 COBJS-$(CONFIG_USB_TTY) += usbtty.o
 
 COBJS	:= $(sort $(COBJS-y))

include/asm-arm/arch-lpc178x/lpc178x.h

@@ -46,6 +46,97 @@
 #define LPC178X_APB0PERIPH_BASE		(LPC178X_APB_PERIPH_BASE + 0x00000000)
 #define LPC178X_APB1PERIPH_BASE		(LPC178X_APB_PERIPH_BASE + 0x00080000)
 
+/*
+ * 1-bit masks for PCONP (Power Control for Peripherals register) for different
+ * peripherals that enable power on them. One of these masks should be passed
+ * as the first argument of `lpc178x_periph_enable`.
+ */
+#define LPC178X_SCC_PCONP_PCUART0_MSK	(1 << 3)
+#define LPC178X_SCC_PCONP_PCUART1_MSK	(1 << 4)
+#define LPC178X_SCC_PCONP_PCUART4_MSK	(1 << 8)
+#define LPC178X_SCC_PCONP_PCUART2_MSK	(1 << 24)
+#define LPC178X_SCC_PCONP_PCUART3_MSK	(1 << 25)
+
+/*
+ * PLL register map
+ * Used for PLL0 at 0x400FC080 and for PLL1 at 0x400FC0A0.
+ */
+struct lpc178x_pll_regs {
+	u32 con;	/* PLL Control register */
+	u32 cfg;	/* PLL Configuration register */
+	u32 stat;	/* PLL Status register */
+	u32 feed;	/* PLL Feed register */
+};
+
+/*
+ * SCC (System and Clock Control) register map
+ * Should be mapped at 0x400FC000.
+ *
+ * This structure is used by the code in `clock.c` and `power.c`.
+ */
+/*
+ * TODO: convert to STM32/SmartFusion structure style,
+ * i.e. use "rsvN[M]" hole fillers instead of "union"s for alignment.
+ * (Not doing this until most lpc178x device drivers are implemented
+ * and all necessary registers in this structure are known.)
+ */
+struct lpc178x_scc_regs {
+	/* 0x400FC000: Flash Accelerator Configuration Register */
+	union {
+		u8 align0[0x80];
+	};
+
+	/* 0x400FC080: PLL0 registers */
+	union {
+		u8 align1[0x20];
+		struct lpc178x_pll_regs pll0; /* PLL0 registers */
+	};
+
+	/* 0x400FC0A0: PLL1 registers */
+	union {
+		u8 align2[0x20];
+		struct lpc178x_pll_regs pll1; /* PLL1 registers */
+	};
+
+	/* 0x400FC0C0: Power control registers */
+	union {
+		u8 align3[0x40];
+		struct {
+			u32 pcon;       /* Power Control register */
+			u32 pconp;      /* Power Control for Peripherals */
+		};
+	};
+
+	/* 0x400FC100: Clock control */
+	union {
+		u8 align4[0xA0];
+		struct {
+			u32 emcclksel;	/* External Memory Controller
+						Clock Selection register */
+			u32 cclksel;	/* CPU Clock Selection register */
+			u32 usbclksel;	/* USB Clock Selection register */
+			u32 clksrcsel;	/* Clock Source Selection register */
+		};
+	};
+
+	/* 0x400FC1A0 */
+	u32 scs;	/* System Controls and Status register */
+	u32 rsv0;
+	u32 pclksel;	/* Peripheral Clock Selection register */
+};
+
+/*
+ * SCC registers base
+ */
+#define LPC178X_SCC_BASE		(LPC178X_APB1PERIPH_BASE + 0x0007C000)
+#define LPC178X_SCC			((volatile struct lpc178x_scc_regs *) \
+					LPC178X_SCC_BASE)
+
+/*
+ * Enable or disable power on a peripheral device (timers, UARTs, USB, etc)
+ */
+extern void lpc178x_periph_enable(u32 pconp_mask, int enable);
+
 /*
  * Clocks enumeration
  */

include/configs/ea-lpc1788.h

@@ -64,6 +64,11 @@
  */
 #define CONFIG_ARCH_CPU_INIT
 
+/*
+ * This ensures that the SoC-specific cortex_m3_soc_init() gets invoked.
+ */
+#define CONFIG_ARMCORTEXM3_SOC_INIT
+
 /*
  * Clock configuration (see cpu/arm_cortexm3/lpc178x/clock.c for details)
  */
@@ -171,7 +176,29 @@
 /*
  * Serial console configuration
  */
-#define CONFIG_LPC178X_UART_CONSOLE
+#define CONFIG_SYS_NS16550		1
+#undef CONFIG_NS16550_MIN_FUNCTIONS
+#define CONFIG_SYS_NS16550_SERIAL	1
+/*
+ * Registers are 32-bit. The negative value tells the ns16550 driver that
+ * registers should be post-padded with zeroes (because the CPU is in
+ * little-endian mode.)
+ */
+#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
+/*
+ * UARTs use the LPC178x/7x Peripheral clock
+ */
+#define CONFIG_SYS_NS16550_CLK		clock_get(CLOCK_PCLK)
+#define CONFIG_CONS_INDEX               1
+/*
+ * UART0 registers base: 0x4000C000
+ * UART1 registers base: 0x40010000
+ * UART2 registers base: 0x40098000
+ * UART3 registers base: 0x4009C000
+ * UART4 registers base: 0x400A4000
+ */
+#define CONFIG_LPC178X_UART_PORT	0	/* Used for UART power-on */
+#define CONFIG_SYS_NS16550_COM1         0x4000C000
 
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }