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Sami Nurmenniemi
u-boot-stm32
Commits
c8c5b260
Commit
c8c5b260
authored
Oct 20, 2011
by
Sergei Poselenov
Browse files
Merge branch 'master' of ocean:/SR/git/A2F/u-boot
parents
8cdee17b
c65f8c64
Changes
6
Hide whitespace changes
Inline
Side-by-side
board/stm/stm3220g-eval/board.c
View file @
c8c5b260
...
...
@@ -170,8 +170,8 @@ int misc_init_r(void)
STM32_FSMC
->
cs
[
i
].
bcr
=
CONFIG_SYS_FSMC_FLASH_BCR
;
STM32_FSMC
->
cs
[
i
].
btr
=
CONFIG_SYS_FSMC_FLASH_BTR
;
# if defined(CONFIG_SYS_FSMC_FLASH_BWR)
STM32_FSMC
->
wt
[
i
].
wtr
=
CONFIG_SYS_FSMC_FLASH_BWR
;
# if defined(CONFIG_SYS_FSMC_FLASH_BW
T
R)
STM32_FSMC
->
wt
[
i
].
b
wtr
=
CONFIG_SYS_FSMC_FLASH_BW
T
R
;
# endif
#endif
/* CONFIG_SYS_NO_FLASH */
...
...
@@ -204,8 +204,8 @@ int dram_init(void)
/* Step.1 */
STM32_FSMC
->
cs
[
i
].
bcr
=
CONFIG_SYS_FSMC_PSRAM_BCR
;
STM32_FSMC
->
cs
[
i
].
btr
=
CONFIG_SYS_FSMC_PSRAM_BTR
;
# if defined(CONFIG_SYS_FSMC_PSRAM_BWR)
STM32_FSMC
->
wt
[
i
].
wtr
=
CONFIG_SYS_FSMC_PSRAM_BWR
;
# if defined(CONFIG_SYS_FSMC_PSRAM_BW
T
R)
STM32_FSMC
->
wt
[
i
].
b
wtr
=
CONFIG_SYS_FSMC_PSRAM_BW
T
R
;
# endif
rv
=
stm32f2_gpio_config
(
&
ctrl_gpio
,
STM32F2_GPIO_ROLE_GPOUT
);
...
...
@@ -236,7 +236,7 @@ int dram_init(void)
/* Step.8 */
STM32_FSMC
->
cs
[
i
].
bcr
=
0x00005059
;
STM32_FSMC
->
cs
[
i
].
btr
=
0x100106F2
;
STM32_FSMC
->
wt
[
i
].
wtr
=
0x100107F2
;
STM32_FSMC
->
wt
[
i
].
b
wtr
=
0x100107F2
;
/* Step.9 */
stm32f2_gpout_set
(
&
ctrl_gpio
,
1
);
...
...
cpu/arm_cortexm3/a2f/clock.c
View file @
c8c5b260
...
...
@@ -212,16 +212,10 @@ void clock_init(void)
/*
* Return a clock value for the specified clock.
* Note that we need this function in RAM because it will be used
* during self-upgrade of U-boot into eNMV.
* @param clck id of the clock
* @returns frequency of the clock
*/
unsigned
long
__attribute__
((
section
(
".ramcode"
)))
__attribute__
((
long_call
))
clock_get
(
enum
clock
clck
)
ulong
clock_get
(
enum
clock
clck
)
{
u
nsigned
long
res
=
0
;
ulong
res
=
0
;
if
(
clck
>=
0
&&
clck
<
CLOCK_END
)
{
res
=
clock
[
clck
];
...
...
cpu/arm_cortexm3/a2f/envm.c
View file @
c8c5b260
...
...
@@ -25,20 +25,21 @@
* ENVM control & status registers
*/
struct
mss_envm
{
u
nsigned
int
status
;
u
nsigned
int
control
;
u
nsigned
int
enable
;
u
nsigned
int
reserved0
;
u
nsigned
int
config_0
;
u
nsigned
int
config_1
;
u
nsigned
int
page_status_0
;
u
nsigned
int
page_status_1
;
u
nsigned
int
segment
;
u
nsigned
int
envm_select
;
u
32
status
;
u
32
control
;
u
32
enable
;
u
32
reserved0
;
u
32
config_0
;
u
32
config_1
;
u
32
page_status_0
;
u
32
page_status_1
;
u
32
segment
;
u
32
envm_select
;
};
#define MSS_ENVM_REGS_BASE 0x60100000
#define MSS_ENVM ((volatile struct mss_envm *)(MSS_ENVM_REGS_BASE))
#define MSS_ENVM ((volatile struct mss_envm *) \
(MSS_ENVM_REGS_BASE))
/*
* Base address of the eNVM Flash
...
...
@@ -91,12 +92,9 @@ void envm_init(void)
* Note that we need for this function to reside in RAM since it
* will be used to self-upgrade U-boot in eNMV.
*/
static
int
__attribute__
((
section
(
".ramcode"
)))
static
s32
__attribute__
((
section
(
".ramcode"
)))
mss_envm_exec_cmd
(
unsigned
int
addr
,
unsigned
int
cmd
)
{
unsigned
int
status
;
int
wait
;
/*
* Get the page address.
*/
...
...
@@ -115,29 +113,10 @@ static int __attribute__((section(".ramcode")))
/*
* Wait for the command to finish
*/
for
(
wait
=
0
;
wait
<
MSS_ENVM_MAX_WAIT_CNT
;
wait
++
)
{
status
=
MSS_ENVM
->
status
;
if
(
!
(
status
&
MSS_ENVM_STATUS_BUSY
))
{
break
;
}
/*
* If not done yet, delay
*/
A2F_TIMER
->
timer1_loadval
=
MSS_ENVM_WAIT_INTERVAL
*
(
clock_get
(
CLOCK_PCLK0
)
/
1000000
);
while
(
A2F_TIMER
->
timer1_val
)
;
}
/*
* Check the status
*/
if
(
status
&
MSS_ENVM_STATUS_BUSY
)
{
return
-
1
;
}
while
(
MSS_ENVM
->
status
&
MSS_ENVM_STATUS_BUSY
)
;
if
(
status
&
MSS_ENVM_STATUS_ERROR_MASK
)
{
if
(
MSS_ENVM
->
status
&
MSS_ENVM_STATUS_ERROR_MASK
)
{
/*
* This code below is a workaround for an occurance
* of the write count has exceeded the 10-year retention
...
...
@@ -152,7 +131,7 @@ static int __attribute__((section(".ramcode")))
* on the board I have has that problem, and the code below
* allows to actually program that page with new content.
*/
if
((
status
&
0x180
)
==
0x180
)
{
if
((
MSS_ENVM
->
status
&
0x180
)
==
0x180
)
{
/*
* Assume the page has been programmed successfully
*/
...
...
@@ -172,14 +151,14 @@ static int __attribute__((section(".ramcode")))
* Note that we need for this function to reside in RAM since it
* will be used to self-upgrade U-boot in eNMV.
*/
u
nsigned
int
__attribute__
((
section
(
".ramcode"
)))
u
32
__attribute__
((
section
(
".ramcode"
)))
__attribute__
((
long_call
))
envm_write
(
u
nsigned
int
offset
,
void
*
buf
,
u
nsigned
int
size
)
envm_write
(
u
32
offset
,
void
*
buf
,
u
32
size
)
{
u
nsigned
int
addr
=
MSS_ENVM_BASE
+
offset
;
u
nsigned
char
*
src
=
(
u
nsigned
char
*
)
buf
;
u
nsigned
int
i
,
written
=
0
;
int
ret
=
0
;
u
32
addr
=
MSS_ENVM_BASE
+
offset
;
u
8
*
src
=
(
u
8
*
)
buf
;
u
32
i
,
written
=
0
;
s32
ret
=
0
;
/*
* Check the sanity of the request.
...
...
include/asm-arm/arch-a2f/a2f.h
View file @
c8c5b260
...
...
@@ -128,14 +128,8 @@ enum clock {
/*
* Return a clock value for the specified clock.
* Note that we need this function in RAM because it will be used
* during self-upgrade of U-boot into eNMV.
* @param clck id of the clock
* @returns frequency of the clock
*/
extern
unsigned
long
__attribute__
((
section
(
".ramcode"
)))
__attribute__
((
long_call
))
clock_get
(
enum
clock
clck
);
extern
ulong
clock_get
(
enum
clock
clck
);
#endif
/*_MACH_A2F_H_ */
...
...
include/asm-arm/arch-stm32/stm32.h
View file @
c8c5b260
...
...
@@ -108,7 +108,7 @@ struct stm32_fsmc_regs {
}
cs
[
4
];
u32
rsv0
[
57
];
struct
{
u32
wtr
;
/* Write timing */
u32
b
wtr
;
/* Write timing */
u32
rsv1
;
}
wt
[
4
];
};
...
...
include/configs/stm3220g-eval.h
View file @
c8c5b260
...
...
@@ -120,7 +120,7 @@
#undef CONFIG_SYS_RAM_BURST
#define CONFIG_SYS_FSMC_PSRAM_BCR 0x00005059
#define CONFIG_SYS_FSMC_PSRAM_BTR 0x10000702
#define CONFIG_SYS_FSMC_PSRAM_BWR 0x10000602
#define CONFIG_SYS_FSMC_PSRAM_BW
T
R 0x10000602
#define CONFIG_SYS_RAM_BASE (0x60000000 + \
((CONFIG_SYS_RAM_CS - 1) * 0x4000000))
...
...
@@ -132,7 +132,7 @@
#define CONFIG_SYS_FSMC_FLASH_BCR 0x00005015
#define CONFIG_SYS_FSMC_FLASH_BTR 0x00010903
#define CONFIG_SYS_FSMC_FLASH_BWR 0x00010803
#define CONFIG_SYS_FSMC_FLASH_BW
T
R 0x00010803
#define CONFIG_SYS_FLASH_BANK1_BASE (0x60000000 + \
((CONFIG_SYS_FLASH_CS - 1) * \
...
...
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