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Sami Nurmenniemi
u-boot-stm32
Commits
cf7bffda
Commit
cf7bffda
authored
Oct 07, 2011
by
Yuri Tikhonov
Browse files
RT72064. stm32: fix prefixes (STM32F2->STM32) in constants and API
Signed-off-by:
Yuri Tikhonov
<
yur@emcraft.com
>
parent
e1616ea3
Changes
16
Expand all
Hide whitespace changes
Inline
Side-by-side
board/stm/stm3220g-eval/board.c
View file @
cf7bffda
...
...
@@ -50,19 +50,19 @@
# undef CONFIG_SYS_FSMC_BTR
# undef CONFIG_SYS_FSMC_BWR
# define CONFIG_SYS_RAM_CS 2
# define CONFIG_SYS_FSMC_BCR (STM32
F2
_FSMC_BCR_WREN | \
(STM32
F2
_FSMC_BCR_MWID_16 << \
STM32
F2
_FSMC_BCR_MWID_BIT) | \
STM32
F2
_FSMC_BCR_MBKEN)
# define CONFIG_SYS_FSMC_BTR (1 << STM32
F2
_FSMC_BTR_BUSTURN_BIT) | \
(2 << STM32
F2
_FSMC_BTR_DATAST_BIT)
# define CONFIG_SYS_FSMC_BCR (STM32_FSMC_BCR_WREN |
\
(STM32_FSMC_BCR_MWID_16 << \
STM32_FSMC_BCR_MWID_BIT) | \
STM32_FSMC_BCR_MBKEN)
# define CONFIG_SYS_FSMC_BTR (1 << STM32_FSMC_BTR_BUSTURN_BIT) | \
(2 << STM32_FSMC_BTR_DATAST_BIT)
# endif
/* !CONFIG_SYS_RAM_CS || !CONFIG_SYS_FSMC_BCR || !CONFIG_SYS_FSMC_BTR */
#endif
/* CONFIG_NR_DRAM_BANKS */
/*
* STM32
F2
RCC FSMC specific definitions
* STM32 RCC FSMC specific definitions
*/
#define STM32
F2
_RCC_ENR_FSMC (1 << 0)
/* FSMC module clock */
#define STM32_RCC_ENR_FSMC (1 << 0)
/* FSMC module clock */
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -138,9 +138,9 @@ int dram_init(void)
int
rv
=
0
;
#if (CONFIG_NR_DRAM_BANKS > 0)
volatile
struct
stm32
f2
_fsmc_regs
*
fsmc_regs
;
volatile
struct
stm32
f2
_rcc_regs
*
rcc_regs
;
int
i
;
volatile
struct
stm32_fsmc_regs
*
fsmc_regs
;
volatile
struct
stm32_rcc_regs
*
rcc_regs
;
int
i
;
/*
* Connect GPIOs to FSMC controller
...
...
@@ -155,13 +155,13 @@ int dram_init(void)
/*
* Enable FSMC interface clock
*/
rcc_regs
=
(
struct
stm32
f2
_rcc_regs
*
)
STM32
F2
_RCC_BASE
;
rcc_regs
->
ahb3enr
|=
STM32
F2
_RCC_ENR_FSMC
;
rcc_regs
=
(
struct
stm32_rcc_regs
*
)
STM32_RCC_BASE
;
rcc_regs
->
ahb3enr
|=
STM32_RCC_ENR_FSMC
;
/*
* Configure FSMC
*/
fsmc_regs
=
(
struct
stm32
f2
_fsmc_regs
*
)
STM32
F2
_FSMC_BASE
;
fsmc_regs
=
(
struct
stm32_fsmc_regs
*
)
STM32_FSMC_BASE
;
i
=
CONFIG_SYS_RAM_CS
-
1
;
/*
...
...
@@ -188,13 +188,13 @@ out:
return
rv
;
}
#ifdef CONFIG_STM32
F2
_ETH
#ifdef CONFIG_STM32_ETH
/*
* Register ethernet driver
*/
int
board_eth_init
(
bd_t
*
bis
)
{
return
stm32
f2
_eth_init
(
bis
);
return
stm32_eth_init
(
bis
);
}
#endif
cpu/arm_cortexm3/cpu.c
View file @
cf7bffda
...
...
@@ -52,8 +52,8 @@ int arch_cpu_init(void)
*/
#if defined(CONFIG_SYS_A2F)
gd
->
bd
->
bi_arch_number
=
MACH_TYPE_A2F
;
#elif defined(CONFIG_SYS_STM32
F2
)
gd
->
bd
->
bi_arch_number
=
MACH_TYPE_STM32
F2
;
#elif defined(CONFIG_SYS_STM32)
gd
->
bd
->
bi_arch_number
=
MACH_TYPE_STM32
;
#else
# error "Unsupported Cortex-M3 SOC."
#endif
...
...
cpu/arm_cortexm3/envm.h
View file @
cf7bffda
...
...
@@ -35,12 +35,12 @@ unsigned int
__attribute__
((
long_call
))
envm_write
(
unsigned
int
offset
,
void
*
buf
,
unsigned
int
size
);
#if defined(CONFIG_SYS_STM32
F2
)
#if defined(CONFIG_SYS_STM32)
/*
* Enable instruction cache, prefetch and set the Flash wait latency
* according to the clock configuration used (HCLK value).
*/
void
envm_config
(
u32
wait_states
);
#endif
/* CONFIG_SYS_STM32
F2
*/
#endif
/* CONFIG_SYS_STM32 */
#endif
/* __ENVM_H__ */
cpu/arm_cortexm3/stm32/Makefile
View file @
cf7bffda
...
...
@@ -3,7 +3,7 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2011
# Port to STM32
F2
# Port to STM32
# Yuri Tikhonov, Emcraft Systems, yur@emcraft.com.
#
# See file CREDITS for list of people who contributed to this
...
...
cpu/arm_cortexm3/stm32/clock.c
View file @
cf7bffda
...
...
@@ -25,25 +25,25 @@
#include
"envm.h"
/*
* STM32
F2
Clock configuration is set by the number of CONFIG options.
* STM32 Clock configuration is set by the number of CONFIG options.
*
* Source for system clock must be selected:
* - CONFIG_STM32
F2
_SYS_CLK_HSI: HSI oscillator used as sys clock,
* CONFIG_STM32
F2
_SYS_CLK_HSE: HSE oscillator used as sys clock,
* CONFIG_STM32
F2
_SYS_CLK_PLL: PLL used as sys clock.
* - CONFIG_STM32_SYS_CLK_HSI: HSI oscillator used as sys clock,
* CONFIG_STM32_SYS_CLK_HSE: HSE oscillator used as sys clock,
* CONFIG_STM32_SYS_CLK_PLL: PLL used as sys clock.
*
* In case of CONFIG_STM32
F2
_SYS_CLK_HSE or CONFIG_STM32
F2
_SYS_CLK_PLL with
* CONFIG_STM32
F2
_PLL_SRC_HSE configurations, the following option must be set:
* - CONFIG_STM32
F2
_HSE_HZ: HSE oscillator frequency value.
* In case of CONFIG_STM32_SYS_CLK_HSE or CONFIG_STM32_SYS_CLK_PLL with
* CONFIG_STM32_PLL_SRC_HSE configurations, the following option must be set:
* - CONFIG_STM32_HSE_HZ: HSE oscillator frequency value.
*
* In case of CONFIG_STM32
F2
_SYS_CLK_PLL configuration, the following options
* In case of CONFIG_STM32_SYS_CLK_PLL configuration, the following options
* must be set:
* - CONFIG_STM32
F2
_PLL_SRC_HSI: HSI clock used as PLL clock entry,
* CONFIG_STM32
F2
_PLL_SRC_HSE: HSE clock used as PLL clock entry;
* - CONFIG_STM32
F2
_PLL_M: division factor for PLL input clock;
* - CONFIG_STM32
F2
_PLL_N: multiplication factor for VCO;
* - CONFIG_STM32
F2
_PLL_P: division factor for main system clock;
* - CONFIG_STM32
F2
_PLL_Q: division factor for USB OTG FS, SDIO and RNG clocks.
* - CONFIG_STM32_PLL_SRC_HSI: HSI clock used as PLL clock entry,
* CONFIG_STM32_PLL_SRC_HSE: HSE clock used as PLL clock entry;
* - CONFIG_STM32_PLL_M: division factor for PLL input clock;
* - CONFIG_STM32_PLL_N: multiplication factor for VCO;
* - CONFIG_STM32_PLL_P: division factor for main system clock;
* - CONFIG_STM32_PLL_Q: division factor for USB OTG FS, SDIO and RNG clocks.
* Then:
* Fsys = Fvco / P : PLL general clock output;
* Fvco = Fin * N / M : VCO clock (Fin is the frequency of PLL source);
...
...
@@ -60,42 +60,42 @@
/*
* Check configuration params
*/
#if ((!!defined(CONFIG_STM32
F2
_SYS_CLK_HSI) + \
!!defined(CONFIG_STM32
F2
_SYS_CLK_HSE) + \
!!defined(CONFIG_STM32
F2
_SYS_CLK_PLL)) != 1)
#if ((!!defined(CONFIG_STM32_SYS_CLK_HSI) + \
!!defined(CONFIG_STM32_SYS_CLK_HSE) + \
!!defined(CONFIG_STM32_SYS_CLK_PLL)) != 1)
# error "Incorrect SYS Clock source configuration."
#endif
#if defined(CONFIG_STM32
F2
_SYS_CLK_HSE) || \
(defined(CONFIG_STM32
F2
_SYS_CLK_PLL) && \
defined(CONFIG_STM32
F2
_PLL_SRC_HSE))
# if !defined(CONFIG_STM32
F2
_HSE_HZ)
#if defined(CONFIG_STM32_SYS_CLK_HSE) || \
(defined(CONFIG_STM32_SYS_CLK_PLL) && \
defined(CONFIG_STM32_PLL_SRC_HSE))
# if !defined(CONFIG_STM32_HSE_HZ)
# error "External oscillator HSE value is not set."
# endif
#endif
#if defined(CONFIG_STM32
F2
_SYS_CLK_PLL)
# if ((!!defined(CONFIG_STM32
F2
_PLL_SRC_HSI) + \
!!defined(CONFIG_STM32
F2
_PLL_SRC_HSE)) != 1)
#if defined(CONFIG_STM32_SYS_CLK_PLL)
# if ((!!defined(CONFIG_STM32_PLL_SRC_HSI) + \
!!defined(CONFIG_STM32_PLL_SRC_HSE)) != 1)
# error "Incorrect PLL clock source configuration."
# endif
# if ((!!defined(CONFIG_STM32
F2
_PLL_M) + \
!!defined(CONFIG_STM32
F2
_PLL_N) + \
!!defined(CONFIG_STM32
F2
_PLL_P) + \
!!defined(CONFIG_STM32
F2
_PLL_Q)) != 4)
# if ((!!defined(CONFIG_STM32_PLL_M) +
\
!!defined(CONFIG_STM32_PLL_N) +
\
!!defined(CONFIG_STM32_PLL_P) +
\
!!defined(CONFIG_STM32_PLL_Q)) != 4)
# error "Incomplete PLL configuration."
# endif
# if (CONFIG_STM32
F2
_PLL_M < 2) || (CONFIG_STM32
F2
_PLL_M > 63)
# if (CONFIG_STM32_PLL_M < 2) || (CONFIG_STM32_PLL_M > 63)
# error "Incorrect PLL_M value."
# endif
# if (CONFIG_STM32
F2
_PLL_N < 192) || (CONFIG_STM32
F2
_PLL_N > 432)
# if (CONFIG_STM32_PLL_N < 192) || (CONFIG_STM32_PLL_N > 432)
# error "Incorrect PLL_N value."
# endif
# if (CONFIG_STM32
F2
_PLL_P != 2) && (CONFIG_STM32
F2
_PLL_P != 4) && \
(CONFIG_STM32
F2
_PLL_P != 6) && (CONFIG_STM32
F2
_PLL_P != 8)
# if (CONFIG_STM32_PLL_P != 2) && (CONFIG_STM32_PLL_P != 4) &&
\
(CONFIG_STM32_PLL_P != 6) && (CONFIG_STM32_PLL_P != 8)
# error "Incorrect PLL_P value."
# endif
# if (CONFIG_STM32
F2
_PLL_Q < 4) || (CONFIG_STM32
F2
_PLL_Q > 15)
# if (CONFIG_STM32_PLL_Q < 4) || (CONFIG_STM32_PLL_Q > 15)
# error "Incorrect PLL_Q value."
# endif
#endif
...
...
@@ -103,113 +103,113 @@
/*
* Internal oscillator value
*/
#define STM32
F2
_HSI_HZ 16000000
/* 16 MHz */
#define STM32_HSI_HZ 16000000
/* 16 MHz */
/*
* Get the SYS CLK value according to configuration
*/
#if defined(CONFIG_STM32
F2
_SYS_CLK_HSI)
# define STM32
F2
_SYS_CLK STM32
F2
_HSI_HZ
#elif defined(CONFIG_STM32
F2
_SYS_CLK_HSE)
# define STM32
F2
_SYS_CLK CONFIG_STM32
F2
_HSE_HZ
#if defined(CONFIG_STM32_SYS_CLK_HSI)
# define STM32_SYS_CLK
STM32_HSI_HZ
#elif defined(CONFIG_STM32_SYS_CLK_HSE)
# define STM32_SYS_CLK
CONFIG_STM32_HSE_HZ
#else
# if defined(CONFIG_STM32
F2
_PLL_SRC_HSE)
# define STM32
F2
_PLL_IN_HZ CONFIG_STM32
F2
_HSE_HZ
# if defined(CONFIG_STM32_PLL_SRC_HSE)
# define STM32_PLL_IN_HZ CONFIG_STM32_HSE_HZ
# else
# define STM32
F2
_PLL_IN_HZ STM32
F2
_HSI_HZ
# define STM32_PLL_IN_HZ STM32_HSI_HZ
# endif
# define STM32
F2
_SYS_CLK ((STM32
F2
_PLL_IN_HZ * \
CONFIG_STM32
F2
_PLL_N) / \
(CONFIG_STM32
F2
_PLL_M * \
CONFIG_STM32
F2
_PLL_P))
# define STM32_SYS_CLK
((STM32_PLL_IN_HZ * \
CONFIG_STM32_PLL_N) /
\
(CONFIG_STM32_PLL_M *
\
CONFIG_STM32_PLL_P))
#endif
/*
* Get the Flash latency value for this SYS CLK
*/
# if (STM32
F2
_SYS_CLK > 0) && (STM32
F2
_SYS_CLK <= 30000000)
# define STM32
F2
_FLASH_WS 0
#elif (STM32
F2
_SYS_CLK > 30000000) && (STM32
F2
_SYS_CLK <= 60000000)
# define STM32
F2
_FLASH_WS 1
#elif (STM32
F2
_SYS_CLK > 60000000) && (STM32
F2
_SYS_CLK <= 90000000)
# define STM32
F2
_FLASH_WS 2
#elif (STM32
F2
_SYS_CLK > 90000000) && (STM32
F2
_SYS_CLK <= 120000000)
# define STM32
F2
_FLASH_WS 3
# if (STM32_SYS_CLK > 0) && (STM32_SYS_CLK <= 30000000)
# define STM32_FLASH_WS
0
#elif (STM32_SYS_CLK > 30000000) && (STM32_SYS_CLK <= 60000000)
# define STM32_FLASH_WS
1
#elif (STM32_SYS_CLK > 60000000) && (STM32_SYS_CLK <= 90000000)
# define STM32_FLASH_WS
2
#elif (STM32_SYS_CLK > 90000000) && (STM32_SYS_CLK <= 120000000)
# define STM32_FLASH_WS
3
#else
# error "Incorrect System clock value configuration."
# define STM32
F2
_FLASH_WS 0
/* to avoid compile-time err */
# define STM32_FLASH_WS
0
/* to avoid compile-time err */
#endif
/*
* Offsets and bitmasks of some RCC regs
*/
#define STM32
F2
_RCC_CR_HSEON (1 << 16)
/* HSE clock enable */
#define STM32
F2
_RCC_CR_HSERDY (1 << 17)
/* HSE clock ready */
#define STM32
F2
_RCC_CR_PLLON (1 << 24)
/* PLL clock enable */
#define STM32
F2
_RCC_CR_PLLRDY (1 << 25)
/* PLL clock ready */
#define STM32
F2
_RCC_CFGR_SW_BIT 0
/* System clock switch */
#define STM32
F2
_RCC_CFGR_SW_MSK 0x3
#define STM32
F2
_RCC_CFGR_SWS_BIT 2
/* System clock switch status */
#define STM32
F2
_RCC_CFGR_SWS_MSK 0x3
#define STM32
F2
_RCC_CFGR_SWS_HSI 0x0
#define STM32
F2
_RCC_CFGR_SWS_HSE 0x1
#define STM32
F2
_RCC_CFGR_SWS_PLL 0x2
#define STM32
F2
_RCC_CFGR_HPRE_BIT 4
/* AHB prescaler */
#define STM32
F2
_RCC_CFGR_HPRE_MSK 0xF
#define STM32
F2
_RCC_CFGR_HPRE_DIVNO 0x0
#define STM32
F2
_RCC_CFGR_HPRE_DIV2 0x8
#define STM32
F2
_RCC_CFGR_HPRE_DIV4 0x9
#define STM32
F2
_RCC_CFGR_HPRE_DIV8 0xA
#define STM32
F2
_RCC_CFGR_HPRE_DIV16 0xB
#define STM32
F2
_RCC_CFGR_HPRE_DIV64 0xC
#define STM32
F2
_RCC_CFGR_HPRE_DIV128 0xD
#define STM32
F2
_RCC_CFGR_HPRE_DIV256 0xE
#define STM32
F2
_RCC_CFGR_HPRE_DIV512 0xF
#define STM32
F2
_RCC_CFGR_PPRE1_BIT 10
/* APB Low speed presc (APB1) */
#define STM32
F2
_RCC_CFGR_PPRE1_MSK 0x7
#define STM32
F2
_RCC_CFGR_PPRE1_DIV0 0x0
#define STM32
F2
_RCC_CFGR_PPRE1_DIV2 0x4
#define STM32
F2
_RCC_CFGR_PPRE1_DIV4 0x5
#define STM32
F2
_RCC_CFGR_PPRE1_DIV8 0x6
#define STM32
F2
_RCC_CFGR_PPRE1_DIV16 0x7
#define STM32
F2
_RCC_CFGR_PPRE2_BIT 13
/* APB high-speed presc (APB2)*/
#define STM32
F2
_RCC_CFGR_PPRE2_MSK 0x7
#define STM32
F2
_RCC_CFGR_PPRE2_DIVNO 0x0
#define STM32
F2
_RCC_CFGR_PPRE2_DIV2 0x4
#define STM32
F2
_RCC_CFGR_PPRE2_DIV4 0x5
#define STM32
F2
_RCC_CFGR_PPRE2_DIV8 0x6
#define STM32
F2
_RCC_CFGR_PPRE2_DIV16 0x7
#define STM32
F2
_RCC_PLLCFGR_HSESRC (1 << 22)
/* Main PLL entry clock src */
#define STM32
F2
_RCC_PLLCFGR_PLLM_BIT 0
/* Div factor for input clock */
#define STM32
F2
_RCC_PLLCFGR_PLLM_MSK 0x3F
#define STM32
F2
_RCC_PLLCFGR_PLLN_BIT 6
/* Mult factor for VCO */
#define STM32
F2
_RCC_PLLCFGR_PLLN_MSK 0x1FF
#define STM32
F2
_RCC_PLLCFGR_PLLP_BIT 16
/* Div factor for main sysclk */
#define STM32
F2
_RCC_PLLCFGR_PLLP_MSK 0x3
#define STM32
F2
_RCC_PLLCFGR_PLLQ_BIT 24
/* Div factor for USB,SDIO,.. */
#define STM32
F2
_RCC_PLLCFGR_PLLQ_MSK 0xF
#define STM32_RCC_CR_HSEON (1 << 16)
/* HSE clock enable */
#define STM32_RCC_CR_HSERDY (1 << 17)
/* HSE clock ready */
#define STM32_RCC_CR_PLLON (1 << 24)
/* PLL clock enable */
#define STM32_RCC_CR_PLLRDY (1 << 25)
/* PLL clock ready */
#define STM32_RCC_CFGR_SW_BIT 0
/* System clock switch */
#define STM32_RCC_CFGR_SW_MSK 0x3
#define STM32_RCC_CFGR_SWS_BIT
2
/* System clock switch status */
#define STM32_RCC_CFGR_SWS_MSK
0x3
#define STM32_RCC_CFGR_SWS_HSI
0x0
#define STM32_RCC_CFGR_SWS_HSE
0x1
#define STM32_RCC_CFGR_SWS_PLL
0x2
#define STM32_RCC_CFGR_HPRE_BIT
4
/* AHB prescaler */
#define STM32_RCC_CFGR_HPRE_MSK
0xF
#define STM32_RCC_CFGR_HPRE_DIVNO 0x0
#define STM32_RCC_CFGR_HPRE_DIV2 0x8
#define STM32_RCC_CFGR_HPRE_DIV4 0x9
#define STM32_RCC_CFGR_HPRE_DIV8 0xA
#define STM32_RCC_CFGR_HPRE_DIV16 0xB
#define STM32_RCC_CFGR_HPRE_DIV64 0xC
#define STM32_RCC_CFGR_HPRE_DIV128 0xD
#define STM32_RCC_CFGR_HPRE_DIV256 0xE
#define STM32_RCC_CFGR_HPRE_DIV512 0xF
#define STM32_RCC_CFGR_PPRE1_BIT 10
/* APB Low speed presc (APB1) */
#define STM32_RCC_CFGR_PPRE1_MSK 0x7
#define STM32_RCC_CFGR_PPRE1_DIV0 0x0
#define STM32_RCC_CFGR_PPRE1_DIV2 0x4
#define STM32_RCC_CFGR_PPRE1_DIV4 0x5
#define STM32_RCC_CFGR_PPRE1_DIV8 0x6
#define STM32_RCC_CFGR_PPRE1_DIV16 0x7
#define STM32_RCC_CFGR_PPRE2_BIT 13
/* APB high-speed presc (APB2)*/
#define STM32_RCC_CFGR_PPRE2_MSK 0x7
#define STM32_RCC_CFGR_PPRE2_DIVNO 0x0
#define STM32_RCC_CFGR_PPRE2_DIV2 0x4
#define STM32_RCC_CFGR_PPRE2_DIV4 0x5
#define STM32_RCC_CFGR_PPRE2_DIV8 0x6
#define STM32_RCC_CFGR_PPRE2_DIV16 0x7
#define STM32_RCC_PLLCFGR_HSESRC (1 << 22)
/* Main PLL entry clock src */
#define STM32_RCC_PLLCFGR_PLLM_BIT 0
/* Div factor for input clock */
#define STM32_RCC_PLLCFGR_PLLM_MSK 0x3F
#define STM32_RCC_PLLCFGR_PLLN_BIT 6
/* Mult factor for VCO */
#define STM32_RCC_PLLCFGR_PLLN_MSK 0x1FF
#define STM32_RCC_PLLCFGR_PLLP_BIT 16
/* Div factor for main sysclk */
#define STM32_RCC_PLLCFGR_PLLP_MSK 0x3
#define STM32_RCC_PLLCFGR_PLLQ_BIT 24
/* Div factor for USB,SDIO,.. */
#define STM32_RCC_PLLCFGR_PLLQ_MSK 0xF
/*
* Timeouts (in cycles)
*/
#define STM32
F2
_HSE_STARTUP_TIMEOUT 0x0500
#define STM32_HSE_STARTUP_TIMEOUT 0x0500
/*
* Clock values
*/
static
u32
clock_val
[
CLOCK_END
];
#if !defined(CONFIG_STM32
F2
_SYS_CLK_HSI)
#if !defined(CONFIG_STM32_SYS_CLK_HSI)
/*
* Set-up clock configuration.
*/
...
...
@@ -221,58 +221,58 @@ static void clock_setup(void)
/*
* Enable HSE, and wait it becomes ready
*/
STM32
F2
_RCC
->
cr
|=
STM32
F2
_RCC_CR_HSEON
;
for
(
i
=
0
;
i
<
STM32
F2
_HSE_STARTUP_TIMEOUT
;
i
++
)
{
if
(
STM32
F2
_RCC
->
cr
&
STM32
F2
_RCC_CR_HSERDY
)
STM32_RCC
->
cr
|=
STM32_RCC_CR_HSEON
;
for
(
i
=
0
;
i
<
STM32_HSE_STARTUP_TIMEOUT
;
i
++
)
{
if
(
STM32_RCC
->
cr
&
STM32_RCC_CR_HSERDY
)
break
;
}
if
(
!
(
STM32
F2
_RCC
->
cr
&
STM32
F2
_RCC_CR_HSERDY
))
{
if
(
!
(
STM32_RCC
->
cr
&
STM32_RCC_CR_HSERDY
))
{
/*
* Have no HSE clock
*/
goto
out
;
}
val
=
STM32
F2
_RCC
->
cfgr
;
val
=
STM32_RCC
->
cfgr
;
/*
* HCLK = SYSCLK / 1
*/
val
&=
~
(
STM32
F2
_RCC_CFGR_HPRE_MSK
<<
STM32
F2
_RCC_CFGR_HPRE_BIT
);
val
|=
STM32
F2
_RCC_CFGR_HPRE_DIVNO
<<
STM32
F2
_RCC_CFGR_HPRE_BIT
;
val
&=
~
(
STM32_RCC_CFGR_HPRE_MSK
<<
STM32_RCC_CFGR_HPRE_BIT
);
val
|=
STM32_RCC_CFGR_HPRE_DIVNO
<<
STM32_RCC_CFGR_HPRE_BIT
;
/*
* PCLK2 = HCLK / 2
*/
val
&=
~
(
STM32
F2
_RCC_CFGR_PPRE2_MSK
<<
STM32
F2
_RCC_CFGR_PPRE2_BIT
);
val
|=
STM32
F2
_RCC_CFGR_PPRE2_DIV2
<<
STM32
F2
_RCC_CFGR_PPRE2_BIT
;
val
&=
~
(
STM32_RCC_CFGR_PPRE2_MSK
<<
STM32_RCC_CFGR_PPRE2_BIT
);
val
|=
STM32_RCC_CFGR_PPRE2_DIV2
<<
STM32_RCC_CFGR_PPRE2_BIT
;
/*
* PCLK1 = HCLK / 4
*/
val
&=
~
(
STM32
F2
_RCC_CFGR_PPRE1_MSK
<<
STM32
F2
_RCC_CFGR_PPRE1_BIT
);
val
|=
STM32
F2
_RCC_CFGR_PPRE1_DIV4
<<
STM32
F2
_RCC_CFGR_PPRE1_BIT
;
val
&=
~
(
STM32_RCC_CFGR_PPRE1_MSK
<<
STM32_RCC_CFGR_PPRE1_BIT
);
val
|=
STM32_RCC_CFGR_PPRE1_DIV4
<<
STM32_RCC_CFGR_PPRE1_BIT
;
STM32
F2
_RCC
->
cfgr
=
val
;
STM32_RCC
->
cfgr
=
val
;
# if defined(CONFIG_STM32
F2
_SYS_CLK_PLL)
# if defined(CONFIG_STM32_SYS_CLK_PLL)
/*
* Configure the main PLL
*/
# if defined(CONFIG_STM32
F2
_PLL_SRC_HSE)
val
=
STM32
F2
_RCC_PLLCFGR_HSESRC
;
# if defined(CONFIG_STM32_PLL_SRC_HSE)
val
=
STM32_RCC_PLLCFGR_HSESRC
;
# else
val
=
0
;
# endif
val
|=
CONFIG_STM32
F2
_PLL_M
<<
STM32
F2
_RCC_PLLCFGR_PLLM_BIT
;
val
|=
CONFIG_STM32
F2
_PLL_N
<<
STM32
F2
_RCC_PLLCFGR_PLLN_BIT
;
val
|=
((
CONFIG_STM32
F2
_PLL_P
>>
1
)
-
1
)
<<
STM32
F2
_RCC_PLLCFGR_PLLP_BIT
;
val
|=
CONFIG_STM32
F2
_PLL_Q
<<
STM32
F2
_RCC_PLLCFGR_PLLQ_BIT
;
val
|=
CONFIG_STM32_PLL_M
<<
STM32_RCC_PLLCFGR_PLLM_BIT
;
val
|=
CONFIG_STM32_PLL_N
<<
STM32_RCC_PLLCFGR_PLLN_BIT
;
val
|=
((
CONFIG_STM32_PLL_P
>>
1
)
-
1
)
<<
STM32_RCC_PLLCFGR_PLLP_BIT
;
val
|=
CONFIG_STM32_PLL_Q
<<
STM32_RCC_PLLCFGR_PLLQ_BIT
;
STM32
F2
_RCC
->
pllcfgr
=
val
;
STM32_RCC
->
pllcfgr
=
val
;
/*
* Enable the main PLL, and wait until main PLL becomes ready.
...
...
@@ -280,42 +280,42 @@ static void clock_setup(void)
* PLL to lock is probably not a constant. There's no timeout here in
* STM lib code as well.
*/
STM32
F2
_RCC
->
cr
|=
STM32
F2
_RCC_CR_PLLON
;
while
(
STM32
F2
_RCC
->
cr
&
STM32
F2
_RCC_CR_PLLRDY
);
STM32_RCC
->
cr
|=
STM32_RCC_CR_PLLON
;
while
(
STM32_RCC
->
cr
&
STM32_RCC_CR_PLLRDY
);
/*
* Select PLL as system source if it's setup OK, and HSE otherwise
*/
if
(
!
(
STM32
F2
_RCC
->
cr
&
STM32
F2
_RCC_CR_PLLRDY
))
val
=
STM32
F2
_RCC_CFGR_SWS_PLL
;
if
(
!
(
STM32_RCC
->
cr
&
STM32_RCC_CR_PLLRDY
))
val
=
STM32_RCC_CFGR_SWS_PLL
;
else
val
=
STM32
F2
_RCC_CFGR_SWS_HSE
;
val
=
STM32_RCC_CFGR_SWS_HSE
;
# else
/*
* Select HSE as system source
*/
val
=
STM32
F2
_RCC_CFGR_SWS_HSE
;
# endif
/* CONFIG_STM32
F2
_SYS_CLK_PLL */
val
=
STM32_RCC_CFGR_SWS_HSE
;
# endif
/* CONFIG_STM32_SYS_CLK_PLL */
/*
* Configure Flash prefetch, Instruction cache, and wait
* latency.
*/
envm_config
(
STM32
F2
_FLASH_WS
);
envm_config
(
STM32_FLASH_WS
);
/*
* Change system clock source, and wait (infinite!) till it done
*/
STM32
F2
_RCC
->
cfgr
&=
~
(
STM32
F2
_RCC_CFGR_SW_MSK
<<
STM32
F2
_RCC_CFGR_SW_BIT
);
STM32
F2
_RCC
->
cfgr
|=
val
<<
STM32
F2
_RCC_CFGR_SW_BIT
;
while
((
STM32
F2
_RCC
->
cfgr
&
(
STM32
F2
_RCC_CFGR_SWS_MSK
<<
STM32
F2
_RCC_CFGR_SWS_BIT
))
!=
(
val
<<
STM32
F2
_RCC_CFGR_SWS_BIT
));
STM32_RCC
->
cfgr
&=
~
(
STM32_RCC_CFGR_SW_MSK
<<
STM32_RCC_CFGR_SW_BIT
);
STM32_RCC
->
cfgr
|=
val
<<
STM32_RCC_CFGR_SW_BIT
;
while
((
STM32_RCC
->
cfgr
&
(
STM32_RCC_CFGR_SWS_MSK
<<
STM32_RCC_CFGR_SWS_BIT
))
!=
(
val
<<
STM32_RCC_CFGR_SWS_BIT
));
out:
return
;
}
#endif
/* CONFIG_STM32
F2
_SYS_CLK_HSI */
#endif
/* CONFIG_STM32_SYS_CLK_HSI */
/*
* Initialize the reference clocks.
...
...
@@ -327,7 +327,7 @@ void clock_init(void)
u32
tmp
,
presc
,
pllvco
,
pllp
,
pllm
;
#if !defined(CONFIG_STM32
F2
_SYS_CLK_HSI)
#if !defined(CONFIG_STM32_SYS_CLK_HSI)
/*
* Set clocks to cfg, which is differs from the poweron default
*/
...
...
@@ -336,75 +336,75 @@ void clock_init(void)
/*
* For consistency with !HSI configs, enable prefetch and cache
*/
envm_config
(
STM32
F2
_FLASH_WS
);
envm_config
(
STM32_FLASH_WS
);
#endif
/*
* Get SYSCLK
*/
tmp
=
STM32
F2
_RCC
->
cfgr
>>
STM32
F2
_RCC_CFGR_SWS_BIT
;
tmp
&=
STM32
F2
_RCC_CFGR_SWS_MSK
;
tmp
=
STM32_RCC
->
cfgr
>>
STM32_RCC_CFGR_SWS_BIT
;
tmp
&=
STM32_RCC_CFGR_SWS_MSK
;
switch
(
tmp
)
{
case
STM32
F2
_RCC_CFGR_SWS_HSI
:
case
STM32_RCC_CFGR_SWS_HSI
:
/* HSI used as system clock source */
clock_val
[
CLOCK_SYSCLK
]
=
STM32
F2
_HSI_HZ
;
clock_val
[
CLOCK_SYSCLK
]
=
STM32_HSI_HZ
;
break
;
case
STM32
F2
_RCC_CFGR_SWS_HSE
:
case
STM32_RCC_CFGR_SWS_HSE
:
/* HSE used as system clock source */
clock_val
[
CLOCK_SYSCLK
]
=
CONFIG_STM32
F2
_HSE_HZ
;
clock_val
[
CLOCK_SYSCLK
]
=
CONFIG_STM32_HSE_HZ
;
break
;
case
STM32
F2
_RCC_CFGR_SWS_PLL
:
case
STM32_RCC_CFGR_SWS_PLL
:
/* PLL used as system clock source */
/*
* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
* SYSCLK = PLL_VCO / PLLP
*/
pllm
=
STM32
F2
_RCC
->
pllcfgr
>>
STM32
F2
_RCC_PLLCFGR_PLLM_BIT
;
pllm
&=
STM32
F2
_RCC_PLLCFGR_PLLM_MSK
;
pllm
=
STM32_RCC
->
pllcfgr
>>
STM32_RCC_PLLCFGR_PLLM_BIT
;
pllm
&=
STM32_RCC_PLLCFGR_PLLM_MSK
;
if
(
STM32
F2
_RCC
->
pllcfgr
&
STM32
F2
_RCC_PLLCFGR_HSESRC
)
{
if
(
STM32_RCC
->
pllcfgr
&
STM32_RCC_PLLCFGR_HSESRC
)
{
/* HSE used as PLL clock source */
tmp
=
CONFIG_STM32
F2
_HSE_HZ
;
tmp
=
CONFIG_STM32_HSE_HZ
;
}
else
{
/* HSI used as PLL clock source */
tmp
=
STM32
F2
_HSI_HZ
;
tmp
=
STM32_HSI_HZ
;
}
pllvco
=
STM32
F2
_RCC
->
pllcfgr
>>
STM32
F2
_RCC_PLLCFGR_PLLN_BIT
;
pllvco
&=
STM32
F2
_RCC_PLLCFGR_PLLN_MSK
;
pllvco
=
STM32_RCC
->
pllcfgr
>>
STM32_RCC_PLLCFGR_PLLN_BIT
;
pllvco
&=
STM32_RCC_PLLCFGR_PLLN_MSK
;
pllvco
*=
tmp
/
pllm
;
pllp
=
STM32
F2
_RCC
->
pllcfgr
>>
STM32
F2
_RCC_PLLCFGR_PLLP_BIT
;
pllp
&=
STM32
F2
_RCC_PLLCFGR_PLLP_MSK
;
pllp
=
STM32_RCC
->
pllcfgr
>>
STM32_RCC_PLLCFGR_PLLP_BIT
;
pllp
&=
STM32_RCC_PLLCFGR_PLLP_MSK
;
pllp
=
(
pllp
+
1
)
*
2
;
clock_val
[
CLOCK_SYSCLK
]
=
pllvco
/
pllp
;
break
;
default:
clock_val
[
CLOCK_SYSCLK
]
=
STM32
F2
_HSI_HZ
;
clock_val
[
CLOCK_SYSCLK
]
=
STM32_HSI_HZ
;
break
;
}
/*
* Get HCLK
*/
tmp
=
STM32
F2
_RCC
->
cfgr
>>
STM32
F2
_RCC_CFGR_HPRE_BIT
;
tmp
&=
STM32
F2
_RCC_CFGR_HPRE_MSK
;
tmp
=
STM32_RCC
->
cfgr
>>
STM32_RCC_CFGR_HPRE_BIT
;
tmp
&=
STM32_RCC_CFGR_HPRE_MSK
;