Commit d5bfc432 authored by Vladimir Khusainov's avatar Vladimir Khusainov
Browse files

RT77469 Added support for the Emcraft SmartFusion SOM to U-boot.

At this point, U-boot just builds. No validation on the target was
performed so far.
parent 50afe39a
......@@ -3200,6 +3200,9 @@ smdkc100_config: unconfig
a2f-lnx-evb_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 a2f-lnx-evb emcraft a2f
a2f-som_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 a2f-som emcraft a2f
a2f-actel-dev-brd_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 a2f-actel-dev-brd \
actel a2f
......
#
# (C) Copyright 2010, 2011
# Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := board.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
/*
* board/emcraft/a2f-som/board.c
*
* Board specific code the the Emcraft SmartFusion system-on-module (SOM).
*
* Copyright (C) 2012
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* FPGA Fabric may include the PSRAM_IP block, which is used to
* control the signals on the EMC interface to get access to
* the configuration registers of the external PSRAM, which
* allows to put the PSRAM into the faster Page Mode.
* The following data structure and the macros provide access
* to the control registers of PSRAM_IP.
* Note: PSRAM_IP may be accessed only when the EMC interface is
* off. In case PSRAM_IP is instantiated in a FPGA design, EMC
* is disabled (or Libero wouldn't have allowed to instantiate
* PSRAM_IP, since it works on the same signals that are used by EMC).
*/
struct psram_ip {
uint32_t val;
uint32_t data_out;
uint32_t addr;
uint32_t trans;
uint32_t magic;
};
#define PSRAM_IP_BASE 0x40050300
#define PSRAM_IP ((volatile struct psram_ip *)(PSRAM_IP_BASE))
#define PSRAM_IP_MAGIC 0x7777
#define PSRAM_IP_BUSY (1<<31)
/*
* Software flag: PSRAM in Page Mode
*/
static int psram_in_page_mode = 0;
/*
* Check if PSRAM_IP is instantiated, and if so, put PSRAM into Page Mode.
* Enable the EMC interface so we are able to access Flash (and then
* external RAM after dram_init has run).
*/
void psram_page_mode(void)
{
unsigned int v;
/*
* Check if the PSRAM_IP IP block is there in the FPGA fabric.
*/
if (PSRAM_IP->magic == PSRAM_IP_MAGIC) {
/*
* Switch the EMC signals into FPGA mode.
*/
A2F_SYSREG->emc_mux_cr &= ~CONFIG_SYS_EMCMUXCR;
/*
* If so, perform the sequence to put PSRAM into Page Mode.
*/
PSRAM_IP->addr = 0xFFFFFFFF;
PSRAM_IP->trans = 0x10000;
while (PSRAM_IP->data_out & PSRAM_IP_BUSY);
v = PSRAM_IP->data_out;
PSRAM_IP->addr = 0xFFFFFFFF;
PSRAM_IP->val = 0x90;
PSRAM_IP->trans = 0x0;
while (PSRAM_IP->data_out & PSRAM_IP_BUSY);
PSRAM_IP->addr = 0xFFFFFFFF;
PSRAM_IP->trans = 0x10000;
while (PSRAM_IP->data_out & PSRAM_IP_BUSY);
v = PSRAM_IP->data_out;
/*
* If PSRAM has been successfully put into Page Mode,
* remember this in a software flag.
*/
if (v == 0x90) {
psram_in_page_mode = 1;
}
}
/*
* Release the EMC from reset. It may have been put
* into reset by a design that installs the IP core
* for setting the external PSRAM into Page Mode.
*/
A2F_SYSREG->soft_rst_cr &= ~(1<<3);
/*
* External memory controller MUX configuration
* The EMC _SEL bit in the EMC_MUX_CR register is used
* to select either FPGA I/O or EMC I/O.
* 1 -> The multiplexed I/Os are allocated to the EMC.
*/
A2F_SYSREG->emc_mux_cr = CONFIG_SYS_EMCMUXCR;
/*
* EMC timing parameters for chip select 1
* where the external Flash memory resides on A2F-LNX-EVB.
* We need to enable the Flash because env_init will
* run soon (which needs to access the Flash).
*/
A2F_SYSREG->emc_cs_1_cr = CONFIG_SYS_EMC0CS1CR;
}
int board_init(void)
{
psram_page_mode();
return 0;
}
int checkboard(void)
{
printf("Board: A2F-SOM Rev %s, www.emcraft.com\n",
CONFIG_SYS_BOARD_REV_STR);
return 0;
}
int dram_init (void)
{
#if ( CONFIG_NR_DRAM_BANKS > 0 )
/*
* EMC timing parameters for chip select 0
* where the external SRAM memory resides on A2F-LNX-EVB.
* The settings depend on whether we have put PSRAM
* into Page Mode or not.
*/
A2F_SYSREG->emc_cs_0_cr = psram_in_page_mode ?
CONFIG_SYS_EMC0CS0CR_PM :
CONFIG_SYS_EMC0CS0CR;
/*
* Fill in global info with description of SRAM configuration.
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
#endif
return 0;
}
int misc_init_r(void)
{
return 0;
}
#ifdef CONFIG_CORE10100
int board_eth_init(bd_t *bis)
{
core_eth_init(bis);
return 0;
}
#endif
/*
* (C) Copyright 2012 Emcraft Systems
*
* Configuration settings for Emcraft Systems'
* SmartFusion system-on-module (SOM).
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Disable debug messages
*/
#undef DEBUG
/*
* This is an ARM Cortex-M3 CPU core
*/
#define CONFIG_SYS_ARMCORTEXM3
/*
* This is the Actel SmartFusion (aka A2F) device
*/
#define CONFIG_SYS_A2F
/*
* This is a specific revision of the board
*/
#define CONFIG_SYS_BOARD_REV 0x1A
#if (CONFIG_SYS_BOARD_REV!=0x1A)
#error CONFIG_SYS_BOARD_REV must be 1A
#endif
/*
* This is a specific SOM variant
*/
#define CONFIG_SYS_SOM_VARIANT 0xA2F500
#if (CONFIG_SYS_SOM_VARIANT!=0xA2F200 && CONFIG_SYS_SOM_VARIANT!=0xA2F500)
#error CONFIG_SYS_SOM_VARIANT must be A2F200 or A2F500
#endif
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_SYS_BOARD_REV_STR "1.A"
/*
* Monitor prompt
*/
#if (CONFIG_SYS_SOM_VARIANT==0xA2F500)
# define CONFIG_SYS_PROMPT "A2F500-SOM> "
#else
# define CONFIG_SYS_PROMPT "A2F200-SOM> "
#endif
/*
* We want to call the CPU specific initialization
*/
#define CONFIG_ARCH_CPU_INIT
/*
* Number of clock ticks in 1 sec
*/
#define CONFIG_SYS_HZ 1000
/*
* Enable/disable h/w watchdog
*/
#undef CONFIG_HW_WATCHDOG
/*
* No interrupts
*/
#undef CONFIG_USE_IRQ
/*
* Memory layout configuration
*/
#define CONFIG_MEM_NVM_BASE 0x00000000
#if (CONFIG_SYS_SOM_VARIANT==0xA2F500)
# define CONFIG_MEM_NVM_LEN (512 * 1024)
#else
# define CONFIG_MEM_NVM_LEN (256 * 1024)
#endif
#define CONFIG_MEM_RAM_BASE 0x20000000
#define CONFIG_MEM_RAM_LEN (16 * 1024)
#define CONFIG_MEM_RAM_BUF_LEN (32 * 1024)
#define CONFIG_MEM_MALLOC_LEN (12 * 1024)
#define CONFIG_MEM_STACK_LEN (4 * 1024)
/*
* malloc() pool size
*/
#define CONFIG_SYS_MALLOC_LEN CONFIG_MEM_MALLOC_LEN
/*
* Configuration of the external memory
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_BASE 0x70000000
#define CONFIG_SYS_RAM_SIZE (16 * 1024 * 1024)
/*
* External Memory Controller settings
* Slow, safe timings for external SRAM
#define CONFIG_SYS_EMC0CS0CR 0x00002aad
*/
/*
* Optimized timings for external SRAM
*/
#define CONFIG_SYS_EMC0CS0CR 0x00002225
/*
* Optimized timings for external SRAM in Page Mode
*/
#define CONFIG_SYS_EMC0CS0CR_PM 0x000020A5
/*
* Settings for the EMC MUX register
*/
#define CONFIG_SYS_EMCMUXCR 0x00000001
/*
* Configuration of the external Flash
*/
#define CONFIG_SYS_FLASH_BANK1_BASE 0x74000000
/*
* Timings for the external Flash
*/
#define CONFIG_SYS_EMC0CS1CR 0x00011137
/*
* Settings for the CFI Flash driver
*/
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BANK1_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
/*
* U-boot environment configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BANK1_BASE
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_INFERNO 1
#define CONFIG_ENV_OVERWRITE 1
/*
* Serial console configuration
*/
#define CONFIG_SYS_NS16550 1
#undef CONFIG_NS16550_MIN_FUNCTIONS
#define CONFIG_SYS_NS16550_SERIAL 1
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK clock_get(CLOCK_PCLK0)
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 0x40000000
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Console I/O buffer size
*/
#define CONFIG_SYS_CBSIZE 256
/*
* Print buffer size
*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/*
* Ethernet driver configuration
*/
#define CONFIG_NET_MULTI
#define CONFIG_CORE10100 1
/*
* Keep Rx & Tx buffers in internal RAM
*/
#define CONFIG_CORE10100_INTRAM_ADDRESS 0x20008000
#define CONFIG_BITBANGMII 1
#define CONFIG_BITBANGMII_MULTI 1
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_RAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_RAM_BASE + \
CONFIG_SYS_RAM_SIZE)
/*
* Needed by "loadb"
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_RAM_BASE
/*
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
*/
#define CONFIG_SYS_MONITOR_BASE 0x0
/*
* Monitor is not in flash. Needs to define this to prevent
* U-Boot from running flash_protect() on the monitor code.
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
/*
* Enable all those monitor commands that are needed
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BOOTD
#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_ECHO
#undef CONFIG_CMD_EDITENV
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_ITEST
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_MISC
#define CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
/*
* To save memory disable long help
*/
#undef CONFIG_SYS_LONGHELP
/*
* Max number of command args
*/
#define CONFIG_SYS_MAXARGS 16
/*
* Auto-boot sequence configuration
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_HOSTNAME a2f-lnx-evb
#if (CONFIG_SYS_SOM_VARIANT==0xA2F500)
# define CONFIG_BOOTARGS "a2f_platform=a2f500-som "\
"console=ttyS0,115200 panic=10"
#else
# define CONFIG_BOOTARGS "a2f_platform=a2f200-som "\
"console=ttyS0,115200 panic=10"
#endif
#define CONFIG_BOOTCOMMAND "run flashboot"
/*
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=70000000\0" \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
"flashaddr=74020000\0" \
"flashboot=run addip;bootm ${flashaddr}\0" \
"ethaddr=C0:B1:3C:88:88:88\0" \
"ipaddr=172.17.4.206\0" \
"serverip=172.17.0.1\0" \
"image=a2f/uImage\0" \
"netboot=tftp ${image};run addip;bootm\0" \
"update=tftp ${image};" \
"prot off ${flashaddr} +${filesize};" \
"era ${flashaddr} +${filesize};" \
"cp.b ${loadaddr} ${flashaddr} ${filesize}\0"
/*
* Linux kernel boot parameters configuration
*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#endif /* __CONFIG_H */
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