Commit db597b14 authored by Alexander Potashev's avatar Alexander Potashev
Browse files

RT77788. k70-som: Support both 120MHz and 150MHz K61/K70 MCUs

 * Add build-time U-Boot option CONFIG_KINETIS_120MHZ or
CONFIG_KINETIS_150MHZ to define the maximum core clock rate of the MCU.
 * Use different PLL configurations to reach to maximum clock rates and
performance.
 * Use different LPDDR timings depending on the clock rate.
 * Use different clock dividers for internal flash and external NAND
flash, as required by the respective datasheets.
parent b7f1415c
......@@ -546,6 +546,8 @@ int misc_init_r(void)
* MT46H32M16LFBF-5
* MT46H32M16LFBF-6
*/
#if defined(CONFIG_KINETIS_120MHZ)
/* DDR clock rate is 120MHz */
#define KINETIS_DDR_INITAREF 2
#define KINETIS_DDR_TINIT 50
#define KINETIS_DDR_TCCD 2
......@@ -579,9 +581,58 @@ int misc_init_r(void)
#define KINETIS_DDR_CKSRX 3
#define KINETIS_DDR_CKSRE 3
#define KINETIS_DDR_APREBIT 10
#define KINETIS_DDR_COLSIZ 1
#define KINETIS_DDR_ADDPINS 3
#define KINETIS_DDR_CMDAGE 255
#define KINETIS_DDR_AGECNT 255
#define KINETIS_DDR_R2WSAME 2
#define KINETIS_DDR_R2RSAME 3
#define KINETIS_DDR_RDDTENBAS 1
#define KINETIS_DDR_PHYRDLAT 6
#define KINETIS_DDR_PYWRLTBS 1
#define KINETIS_DDR_CTRLUPDMX 968
#define KINETIS_DDR_PHYUPDTY1 968
#define KINETIS_DDR_PHYUPDTY0 968
#define KINETIS_DDR_PHYUPDTY3 968
#define KINETIS_DDR_PHYUPDTY2 968
#define KINETIS_DDR_WRLATADJ 2
#define KINETIS_DDR_RDLATADJ 3
#define KINETIS_DDR_PHYUPDRESP 968
#define KINETIS_DDR_CLKENDLY 1
#define KINETIS_DDR_CMDDLY 2
#elif defined(CONFIG_KINETIS_150MHZ)
/* DDR clock rate is 150MHz */
#define KINETIS_DDR_INITAREF 2
#define KINETIS_DDR_TINIT 50
#define KINETIS_DDR_TCCD 2
#define KINETIS_DDR_WRLAT 1
#define KINETIS_DDR_LATGATE 6
#define KINETIS_DDR_LATLIN 6
#define KINETIS_DDR_TRASMIN 7
#define KINETIS_DDR_TRC 10
#define KINETIS_DDR_TRRD 2
#define KINETIS_DDR_TBINT 1
#define KINETIS_DDR_TMRD 2
#define KINETIS_DDR_TRTP 2
#define KINETIS_DDR_TRP 3
#define KINETIS_DDR_TWTR 2
#define KINETIS_DDR_TRASMAX 10500 /* 70 us */
#define KINETIS_DDR_TMOD 0
#define KINETIS_DDR_TCKESR 1
#define KINETIS_DDR_CLKPW 1
#define KINETIS_DDR_TDAL 6
#define KINETIS_DDR_TWR 3
#define KINETIS_DDR_TRASDI 3
#define KINETIS_DDR_TDLL 0
#define KINETIS_DDR_TRPAB 3
#define KINETIS_DDR_TCPD 30000
#define KINETIS_DDR_TFAW 0
#define KINETIS_DDR_TREF 1170 /* 7.8 us */
#define KINETIS_DDR_TRFC 15
#define KINETIS_DDR_TXSR 19
#define KINETIS_DDR_TPDEX 2
#define KINETIS_DDR_TXSNR 19
#define KINETIS_DDR_CKSRX 3
#define KINETIS_DDR_CKSRE 3
#define KINETIS_DDR_CMDAGE 255
#define KINETIS_DDR_AGECNT 255
......@@ -601,6 +652,15 @@ int misc_init_r(void)
#define KINETIS_DDR_CLKENDLY 1
#define KINETIS_DDR_CMDDLY 2
#endif /* 120MHz / 150MHz */
/*
* Parameters that defined address mapping
*/
#define KINETIS_DDR_APREBIT 10
#define KINETIS_DDR_COLSIZ 1
#define KINETIS_DDR_ADDPINS 3
/*
* LPDDR memory chip configuration options
*/
......
......@@ -99,6 +99,7 @@
#endif
#elif defined(CONFIG_KINETIS_K70_120MHZ)
/* MCUs with maximum core rate 120MHz or 150MHz */
#define KINETIS_PLL_PRDIV_MAX 8
#define KINETIS_PLL_VDIV_MIN 16
#define KINETIS_PLL_VDIV_MAX 47
......@@ -108,11 +109,20 @@
#define KINETIS_PLL_VCO_DIV 2 /* There is a /2 divider after VCO */
#if defined(CONFIG_KINETIS_120MHZ)
/* 120MHz */
#define KINETIS_CPU_RATE_MAX (120 * 1000 * 1000) /* 120 MHz */
#define KINETIS_PCLK_RATE_MAX (60 * 1000 * 1000) /* 60 MHz */
#define KINETIS_DDR_RATE_MAX (125 * 1000 * 1000) /* 125 MHz */
#elif defined(CONFIG_KINETIS_150MHZ)
/* 150MHz */
#define KINETIS_CPU_RATE_MAX (150 * 1000 * 1000) /* 150 MHz */
#define KINETIS_PCLK_RATE_MAX (75 * 1000 * 1000) /* 75 MHz */
#define KINETIS_DDR_RATE_MAX (150 * 1000 * 1000) /* 150 MHz */
#endif
#define KINETIS_FLEXBUS_RATE_MAX (50 * 1000 * 1000) /* 50 MHz */
#define KINETIS_FLASH_RATE_MAX (25 * 1000 * 1000) /* 25 MHz */
#define KINETIS_DDR_RATE_MAX (150 * 1000 * 1000) /* 150 MHz */
#define KINETIS_MCG_PLLREFSEL 0 /* PLL0/1 input: EXTAL0 through OSC0 */
......
......@@ -43,9 +43,10 @@
#define CONFIG_SYS_KINETIS
/*
* Choose Kinetis MCU family
* Choose Kinetis MCU family and maximum core frequency
*/
#define CONFIG_KINETIS_K70
#define CONFIG_KINETIS_120MHZ
/*
* Enable GPIO driver
......@@ -122,12 +123,17 @@
* constant should be as close to the 32..40 kHz range as possible.
*/
#define KINETIS_MCG_FRDIV_POW 10
/* Core/system clock divider: 120/1 = 120 MHz */
/* Core/system clock divider: 120/1 = 120MHz or 150/1 = 150MHz */
#define KINETIS_CCLK_DIV 1
/* Peripheral clock divider: 120/2 = 60 MHz */
/* Peripheral clock divider: 120/2 = 60MHz or 150/2 = 75MHz */
#define KINETIS_PCLK_DIV 2
/* FlexBus clock divider: 120/3 = 40 MHz */
/* FlexBus clock divider: 120/3 = 40MHz or 150/3 = 50MHz */
#define KINETIS_FLEXBUS_CLK_DIV 3
#if defined(CONFIG_KINETIS_120MHZ)
/*
* 120MHz MCU
*/
/* Flash clock divider: 120/5 = 24 MHz */
#define KINETIS_FLASH_CLK_DIV 5
/* NFC clock divider: PLL0/7 = 120/7 = 17.14 MHz */
......@@ -150,6 +156,36 @@
#define KINETIS_PLL1_PRDIV 5
/* PLL1 multiplier: 10*24/2 = 120 MHz */
#define KINETIS_PLL1_VDIV 24
#elif defined(CONFIG_KINETIS_150MHZ)
/*
* 150MHz MCU
*/
/* Flash clock divider: 150/6 = 25 MHz */
#define KINETIS_FLASH_CLK_DIV 6
/* NFC clock divider: PLL0/8 = 150/8 = 18.75 MHz */
#define KINETIS_NFCCLK_DIV 8
/* NFC clock fraction: do no multiply */
#define KINETIS_NFCCLK_FRAC 1
#ifdef KINETIS_HAS_LCD
/* LCDC clock divider: PLL/5 = 150/5 = 30 MHz */
#define KINETIS_LCDCCLK_DIV 5
/* LCDC clock fraction: do no multiply */
#define KINETIS_LCDCCLK_FRAC 1
#endif /* KINETIS_HAS_LCD */
/* PLL input divider: 50/5 = 10 MHz */
#define KINETIS_PLL_PRDIV 5
/* PLL multiplier: 10*30/2 = 150 MHz */
#define KINETIS_PLL_VDIV 30
/* PLL1 input divider: 50/5 = 10 MHz */
#define KINETIS_PLL1_PRDIV 5
/* PLL1 multiplier: 10*30/2 = 150 MHz */
#define KINETIS_PLL1_VDIV 30
#endif
/* Use PLL1 for MCGOUT (required for synchronous mode of the DDR controller) */
#define KINETIS_MCGOUT_PLL1
/*
......
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