RT74765. twr-k60n512: Fix a bug; increase configurability of `mcffec`

The value for the RCR (Receive Control Register) was wrong in the
half-duplex mode.

The `mcf*` targets were not checked for clean build.

drivers/net/fec.h

@@ -305,6 +305,7 @@ typedef struct fec {
 
 /* Bit definitions and macros for FEC_RCR */
 #define FEC_RCR_MAX_FL(x)		(((x)&0x7FF)<<16)
+#define FEC_RCR_RMII_MODE		(0x00000100)
 #define FEC_RCR_FCE			(0x00000020)
 #define FEC_RCR_BC_REJ			(0x00000010)
 #define FEC_RCR_PROM			(0x00000008)

drivers/net/mcffec.c

@@ -106,15 +106,18 @@ void fec_reset(struct eth_device *dev);
 
 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
 {
+	/* Set maximum frame length */
+	fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE;
+#ifndef CONFIG_MCFFEC_MII
+	fecp->rcr |= FEC_RCR_RMII_MODE;
+#endif
+
 	if ((dup_spd >> 16) == FULL) {
-		/* Set maximum frame length */
-		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
-		    FEC_RCR_PROM | 0x100;
+		/* Full duplex mode */
 		fecp->tcr = FEC_TCR_FDEN;
 	} else {
 		/* Half duplex mode */
-		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
-		    FEC_RCR_MII_MODE | FEC_RCR_DRT;
+		fecp->rcr |= FEC_RCR_DRT;
 		fecp->tcr &= ~FEC_TCR_FDEN;
 	}
 

drivers/net/mcfmii.c

@@ -60,6 +60,12 @@ DECLARE_GLOBAL_DATA_PTR;
 #	define CONFIG_SYS_UNSPEC_STRID		0
 #endif
 
+/*
+ * The MSCR[MII_SPEED] bit field consists of 6 bits, therefore the maximum
+ * possible value for this field is 63.
+ */
+#define MCFFEC_MII_SPEED_MAX	63
+
 #ifdef CONFIG_MCF547x_8x
 typedef struct fec_info_dma FEC_INFO_T;
 #define FEC_T fecdma_t
@@ -178,7 +184,7 @@ int mii_discover_phy(struct eth_device *dev)
 #ifdef ET_DEBUG
 			printf("PHY type 0x%x pass %d type\n", phytype, pass);
 #endif
-			if (phytype != 0xffff) {
+			if (phytype != 0xffff && phytype != 0) {
 				phyaddr = phyno;
 				phytype <<= 16;
 				phytype |=
@@ -249,7 +255,22 @@ void __mii_init(void)
 	fecp->eir = 0xffffffff;
 
 	/* Set MII speed */
+#ifdef CONFIG_M68K
 	miispd = (gd->bus_clk / 1000000) / 5;
+#else
+	/*
+	 * The MSCR[MII_SPEED] bit field is minus 1 encoded.
+	 *
+	 * We round the value in MSCR[MII_SPEED] up, so that the MDC frequency
+	 * never exceeds CONFIG_MCFFEC_MII_SPEED_LIMIT.
+	 */
+	miispd =
+		(CONFIG_MCFFEC_MAC_CLK - 1) /
+		(2 * CONFIG_MCFFEC_MII_SPEED_LIMIT);
+#endif /* CONFIG_M68K */
+	if (miispd > MCFFEC_MII_SPEED_MAX)
+		miispd = MCFFEC_MII_SPEED_MAX;
+
 	fecp->mscr = miispd << 1;
 
 	info->phy_addr = mii_discover_phy(dev);