RT106081: U-Boot STM32F7. Synchronize D-/I-caches on bootm

This is to avoid 'HARD FAULT' when booting from flash mem having the
'write-back' caching policy. In this case the data copied may remain
in D-cache without flushing them to SDRAM, so on executing such code
we'll fill I-cache with garbage from SDRAM.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

common/cmd_bootm.c

@@ -36,6 +36,7 @@
 #include <lmb.h>
 #include <linux/ctype.h>
 #include <asm/byteorder.h>
+#include <asm/cache.h>
 
 #if defined(CONFIG_CMD_USB)
 #include <usb.h>
@@ -704,6 +705,11 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	arch_preboot_os();
 
+#if defined(CONFIG_STM32F7_DCACHE_ON) && defined(CONFIG_STM32F7_ICACHE_ON)
+	stm32f7_cache_sync_range(images.os.load,
+				 images.os.load + images.os.image_len);
+#endif
+
 	boot_fn(0, argc, argv, &images);
 
 	show_boot_progress (-9);

cpu/arm_cortexm3/stm32/soc.c

@@ -50,6 +50,12 @@
 #define _ICIALLU	*((volatile u32*)(0xE000EF50))
 /* Data cache invalidate by set/way */
 #define _DCISW		*((volatile u32*)(0xE000EF60))
+/* Data cache clean by address to PoU */
+#define _DCCMVAU	*((volatile u32*)(0xE000EF64))
+/* Instruction cache invalidate by address to PoU */
+#define _ICIMVAU	*((volatile u32*)(0xE000EF58))
+/* Branch predictor invalidate all */
+#define _BPIALL		*((volatile u32*)(0xE000EF78))
 
 /*
  * MPU regions. The order below is important: if regions overlap, then
@@ -261,6 +267,27 @@ static void stm32f7_enable_cache(void)
 }
 #endif
 
+#if defined(CONFIG_STM32F7_DCACHE_ON) && defined(CONFIG_STM32F7_ICACHE_ON)
+/*
+ * Clean D-cache, invalidate I-cache, and invalidate B-cache within
+ * the specified region.
+ * - s - start address of region
+ * - e - end address of region
+ */
+void stm32f7_cache_sync_range(u32 s, u32 e)
+{
+	for ( ; s < e; s += CONFIG_SYS_CACHELINE_SIZE) {
+		_DCCMVAU = s;
+		_ICIMVAU = s;
+	}
+
+	_BPIALL = 0;
+
+	__asm__ volatile("dsb");
+	__asm__ volatile("isb");
+}
+#endif
+
 /*
  * SoC configuration code that cannot be put into drivers
  */

include/asm-arm/cache.h

@@ -27,6 +27,15 @@
 
 #include <asm/system.h>
 
+#if defined(CONFIG_STM32F7_DCACHE_ON) && defined(CONFIG_STM32F7_ICACHE_ON)
+/*
+ * Ensure that the I and D caches are coherent within specified
+ * region. This is typically used when code has been written to
+ * a memory region, and will be executed.
+ */
+void stm32f7_cache_sync_range(u32 s, u32 e);
+#endif
+
 /*
  * Invalidate L2 Cache using co-proc instruction
  */

include/configs/stm32f7-som.h

@@ -114,6 +114,7 @@
 /*
  * Cache configuration
  */
+#define CONFIG_SYS_CACHELINE_SIZE	32
 #define CONFIG_STM32F7_ICACHE_ON
 /* #undef CONFIG_STM32F7_ICACHE_ON */
 #define CONFIG_STM32F7_DCACHE_ON