RT106081. STM32F4: fix-up u-boot self-update (with caches on)

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

cpu/arm_cortexm3/stm32/envm.c

@@ -260,9 +260,6 @@ stm32_flash_program(u32 offset, void *buf, u32 size)
 	stm32_flash_cr_unlock();
 	STM32_FLASH_REGS->cr |= STM32_FLASH_CR_PG;
 
-#if defined(CONFIG_STM32F7_DCACHE_ON) || defined(CONFIG_STM32F7_ICACHE_ON)
-	stm32f7_envm_as_dev();
-#endif
 	/* Since we are using 32x parallelism (set in CR), copy by 4 bytes */
 	while (words--) {
 		*dst++ = *src++;
@@ -270,9 +267,7 @@ stm32_flash_program(u32 offset, void *buf, u32 size)
 		while (STM32_FLASH_REGS->sr & STM32_FLASH_SR_BSY)
 			;
 	}
-#if defined(CONFIG_STM32F7_DCACHE_ON) || defined(CONFIG_STM32F7_ICACHE_ON)
-	stm32f7_envm_as_mem();
-#endif
+
 	STM32_FLASH_REGS->cr &= ~STM32_FLASH_CR_PG;
 	stm32_flash_cr_lock();
 
@@ -323,6 +318,9 @@ envm_write(u32 offset, void * buf, u32 size)
 {
 	s32 ret = 0;
 
+#if defined(CONFIG_STM32F7_DCACHE_ON) || defined(CONFIG_STM32F7_ICACHE_ON)
+	stm32f7_envm_as_dev();
+#endif
 	/* Basic sanity check. More checking in the "get_block" routine */
 	if ((offset < STM32_FLASH_BASE) ||
 		((offset + size) > (STM32_FLASH_BASE + STM32_FLASH_SIZE))) {
@@ -338,5 +336,8 @@ envm_write(u32 offset, void * buf, u32 size)
 
 	ret = size;
 xit:
+#if defined(CONFIG_STM32F7_DCACHE_ON) || defined(CONFIG_STM32F7_ICACHE_ON)
+	stm32f7_envm_as_dev();
+#endif
 	return ret;
 }