From ef31bb48a90cf370dcad9ebe375e54b44b555961 Mon Sep 17 00:00:00 2001
From: Sergei Miroshnichenko <sergeimir@emcraft.com>
Date: Thu, 19 Jan 2017 07:23:59 +0300
Subject: [PATCH] RM#1054 stm32: clock: Adjust RCC for high freq LCDs
Default value of RCC_PLLSAICFGR.PLLSAIR=8 doesn't allow to set up
high speed LCD
---
cpu/arm_cortexm3/stm32/clock.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/cpu/arm_cortexm3/stm32/clock.c b/cpu/arm_cortexm3/stm32/clock.c
index bf4da2b9..cfa953fc 100644
--- a/cpu/arm_cortexm3/stm32/clock.c
+++ b/cpu/arm_cortexm3/stm32/clock.c
@@ -224,6 +224,7 @@
#define STM32_RCC_DCKCFGR_PLLSAIDIVR (3 << 16)
#define STM32_RCC_PLLSAIDivR_Div8 (2 << 16)
+#define STM32_RCC_PLLSAIDivR_Div2 (0 << 16)
/*
* Offsets and bitmasks of some PWR regs
@@ -305,6 +306,10 @@ void sai_r_clk_enable(void)
/* Calculate N to match the requested rate */
sai_n = CONFIG_STM32_LTDC_PIXCLK * sai_r * sai_div_r / parent_rate;
+ if (sai_n > STM32_RCC_PLLCFGR_PLLN_MSK) {
+ sai_div_r = 2;
+ sai_n = CONFIG_STM32_LTDC_PIXCLK * sai_r * sai_div_r / parent_rate;
+ }
/* Disable PLLSAI */
sai_r_clk_disable();
@@ -319,7 +324,10 @@ void sai_r_clk_enable(void)
dckcfgr &= ~STM32_RCC_DCKCFGR_PLLSAIDIVR;
/* Set PLLSAIDIVR values */
- dckcfgr |= STM32_RCC_PLLSAIDivR_Div8;
+ if (8 == sai_div_r)
+ dckcfgr |= STM32_RCC_PLLSAIDivR_Div8;
+ else if (2 == sai_div_r)
+ dckcfgr |= STM32_RCC_PLLSAIDivR_Div2;
/* Store the new value */
STM32_RCC->dckcfgr = dckcfgr;
--
GitLab