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in FPGA design.

runs from eNVM. Helps U-boot performance a bit.

that the hardware starts up correctly on reset / power-on.

Revert "RT #80404. Added workaround for Libero bug - initialize iomuxes for"
This reverts commit b38452d4.

Removed the iomux cell initialization workaround, found the real fix -
the FPGA_RPRG pin was incorrectly pulled down on the M2S-SOM module.

modules running at 120 and 150 MHz.

- sf probe 0
- sf read a0000000 100000 f00000
reads a 15MB file into DDR for ~3sec.

UART0 and SPI in U-Boot.

Use only with the respective .stp design!

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Signed-off-by: Vadim Aleynikov <vadim_a@emcraft.com>
Signed-off-by: Alexander Potashev <aspotashev@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

This is required for any code execution (including the Linux kernel) in
the external RAM on SmartFusion2 (M2S).

We will reuse this function on SmartFusion2 (M2S).

There's no compatibility with A2F SPI now, so give the appropriate
names to constants, and funtions.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

In this case DDR Bridge buffering BUG isn't triggered.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

We suspect some BUG in the buffering scheme. See RT records for
details.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

This is to avoid slowing things down, when we'll switch to malloc
in external mem.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

This is more precise.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

This allow to dramatically speed-up xfers on high SPI CLKs (previo-
usly we got stuck at ~ 1MHz; higher clocks gave nothing because of
program CPU execution latencies).
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Use more compact macros to access reags instead of read/write.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Supported:
 - UART0 (57600)
 - SPI0 (non-DMA)
 - Ethernet
 - LPDDR
 - Env in SPI Flash

definition of CONFIG_MEM_NVM_UBOOT_OFF for those U-boot configuraitons
that do not require that macro.

U-boot to run from eNVM at offset 0x20000:

- to program that U-boot to eNVM: cptf 0x20000 ${loadaddr} ${filesize} 0
- to run that U-boot from eNVM: go 20375

are preformed manually, as per the test plan.

Take into account the delay t_{v(A_NE)} (4.5 ns) before the MCU outputs
the chips select signal A[23].

 * In order to switch the MCG to the PLL Engaged External mode (PEE
mode), it must pass the FLL Bypassed External mode (FBE mode) as an
intermediate step. See section `25.4.1 MCG Mode State Diagram` on page
656 of the K70 Reference Manual.
 * Enable and use the RTC clock for FLL when switching to the
FLL Bypassed External mode (FBE mode). We do this in `clock_fei_to_fbe()`
in `u-boot/cpu/arm_cortexm3/kinetis/clock.c` before switching to
the FBE mode. This is required, because:
   * In order to switch to the PLL Engaged External mode (PEE mode), we
must pass the FLL Bypassed External mode (FBE mode).
   * This FBE mode requires that there is a working FLL reference clock.
   * Only OSC0 clock (clock or oscillator at EXTAL0/XTAL0) or RTC clock
(oscillator at EXTAL32/XTAL32) can be used as reference clock for FLL.
   * In the K**-SOM/DNI-ETH configuration, nothing is connected to
EXTAL0, therefore we have to use the RTC clock as reference clock
for FLL in the FBE mode.
 * Use RTC for FLL reference clock only on K**-SOMs, but not for
TWR-K70F120M. To do that, we add a new U-Boot configuration option
`KINETIS_FLLREF_RTC` that will control usage of RTC for FLL reference
clock and define this configuration option only in
`u-boot/include/configs/k70-som.h`.
 * Use in-MCU 20pF oscillator load.

 * Use external oscillator at EXTAL1/XTAL1 as clock source for the main
PLL on K70-SOM.
 * Do not change clock configuration for TWR-K70F120M.

Either CONFIG_KINETIS_120MHZ or CONFIG_KINETIS_150MHZ must be defined.
The TWR-K70F120M board has a 120MHz K70 MCU.