1. 20 Apr, 2012 2 commits
  2. 18 Apr, 2012 1 commit
  3. 11 Apr, 2012 1 commit
    • Alexander Potashev's avatar
      RT77788. k70-som: Add support for the Emcraft K70-SOM + SOM-BSB platform · 065d7e55
      Alexander Potashev authored
       * Add Makefile target `k70-som_config`.
       * Start K70-SOM board support code by cloning off the TWR-K70F120M
      board-specific code.
       * Update DDR controller configuration to interact with the LPDDR memory chip.
      Update timings for a 120 MHz DDR clock.
       * Remove configuration of pins NFC_D8..NFC_D15, they are not used by 8-bit NAND
       * Optionally support 8-bit NAND flashes in the `fsl_nfc.c` driver.
       * Set correct size of RAM (64 MB).
       * Do not configure the LCD clock, because we do not support LCDs with K70-SOM
       * Update U-Boot prompt, IP address, MAC address, bootargs, hostname.
  4. 10 Apr, 2012 3 commits
  5. 09 Apr, 2012 1 commit
    • Alexander Potashev's avatar
      RT76276. Add support for STMicroelectronics STM3240G-EVAL board · f271a6db
      Alexander Potashev authored
      * Clone the board-specific files from those used for the STM3220G-EVAL board.
      * Change STM3220G-EVAL to STM3240G-EVAL where appropriate.
      * cpu/arm_cortexm3/stm32/clock.c: Add support for clock rates up to 168 MHz.
      * Ethernet driver: Implement us/ms delays not tied to CPU clock rate.
      * Ethernet driver: Add `stm_phy_wait_busy()` to reduce code duplication.
      * Raise system clock rate from 120 MHz to 168 MHz.
      * Update PSRAM timings.
      * Disable the PSRAM Synchronous Burst Mode.
  6. 04 Apr, 2012 1 commit
  7. 03 Apr, 2012 1 commit
  8. 30 Mar, 2012 1 commit
  9. 29 Mar, 2012 1 commit
    • Alexander Potashev's avatar
      RT77452. Add support for Emcraft's LPC-LNX-EVB board · 0b0a296c
      Alexander Potashev authored
       * Add Makefile target `lpc-lnx-evb_config`.
       * Configure one more EMC address pin on LPC-LNX-EVB (in comparison to
      EA-LPC1788) to make all 16 MBytes of NOR Flash work.
       * Remove pin configuration for UART2 (compared to EA-LPC1788), it is
      not supported by this board.
       * Disable PLL1 and USB clock configuration.
       * The NOR Flash is CFI-compatible, so we do not need to use
      `CONFIG_FLASH_CFI_LEGACY` unlike EA-LPC1788.
       * Update MAC and IP address.
  10. 19 Mar, 2012 1 commit
  11. 18 Mar, 2012 2 commits
  12. 14 Mar, 2012 1 commit
  13. 12 Mar, 2012 1 commit
  14. 11 Mar, 2012 1 commit
  15. 10 Mar, 2012 1 commit
  16. 08 Mar, 2012 1 commit
  17. 28 Feb, 2012 1 commit
    • Alexander Potashev's avatar
      RT77090. kinetis eth: Fix receiving of Ethernet packets · fe65e8bf
      Alexander Potashev authored
      The Ethernet module of the MCU requires that the RDAR register is set
      only after a while after the RDSR register is set; i.e. the RDAR
      register should not be set immediately after RDSR during initialization
      of the Ethernet module.
        1. If we write to the ENET_RDAR register immediately after initializing
      the ENET_RDSR register, the incoming packets can _never_ be received.
        2. If we make the MCU wait for 10us before writing to ENET_RDAR, the
      incoming packets are _always_ received correctly.
        3. If we perform a few instructions (about 10 of them) between setting
      RDSR and RDAR, then the problem manifests randomly from time to time.
      In order to fix the bug, we add a 10us delay just before writing
      to the RDAR register.
      Things just work in Freescale MQX and in Linux, because there is a lot
      of other initialization code between the RDAR and RDSR register are set,
      so this other initialization code serves as a delay.
  18. 22 Feb, 2012 1 commit
  19. 20 Feb, 2012 1 commit
  20. 10 Feb, 2012 1 commit
    • Alexander Potashev's avatar
      RT76453. twr-k70f120m: make env bad block tolerant · 65d91d4f
      Alexander Potashev authored
       * Use `CONFIG_ENV_RANGE` to let U-Boot use any of the first 4 blocks of the
      NAND flash for storage of the U-Boot environment.
       * Use `CONFIG_ENV_OFFSET_REDUND`: if the block where the main copy of the U-Boot
      environment resides becomes bad, the environment will be restored from the
      redundant copy. Allocate another 4 blocks for the redundant copy of the
       * Update the `flashaddr` variable and the `update` macro in the U-Boot
       * Increase the size of the malloc() pool, needed to use both
      the `CONFIG_ENV_RANGE` and the `CONFIG_ENV_[...]_REDUND` features.
  21. 04 Feb, 2012 1 commit
  22. 31 Jan, 2012 1 commit
  23. 30 Jan, 2012 2 commits
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: configure the DDR controller for synchronous mode · 514d2c27
      Alexander Potashev authored
      There are 3 ports (port 0, port 1, port 2) between the AHB bus and the
      DDR controller. All of these ports are switched to the synchronous mode
      in this patch.
      Any of these 3 ports can work in the synchronous mode only when the
      system clock is sourced from PLL1. Since the DDR clock is also sourced
      from the PLL1 and the CPU clock rate is limited to 120 MHz, we have to
      lower the DDR clock to the same 120 MHz.
      The source code is configurable so that you can easily switch back to
      the DDR asynchronous mode:
       * Synchronous mode configuration (see include/configs/twr-k70f120m.h):
          * KINETIS_PLL1_VDIV = 24 (we have to limit DDR clock to 120 MHz)
          * KINETIS_MCGOUT_PLL1 is set (system clock is sourced from PLL1)
          * CONFIG_KINETIS_DDR_SYNC is set
       * Asynchronous mode configuration (see include/configs/twr-k70f120m.h):
          * KINETIS_PLL1_VDIV = 30 (we want the maximum DDR clock: 150 MHz)
          * KINETIS_MCGOUT_PLL1 is not set (system clock is sourced from PLL0)
          * CONFIG_KINETIS_DDR_SYNC is not set
      The DDR synchronous mode improves performance: 37.27 BogoMIPS in
      synchronous mode (DDR @ 120 MHz) against 11.03 BogoMIPS in asynchronous
      mode (DDR @ 150 MHz) in Linux.
    • Alexander Potashev's avatar
      RT74765, RT75957. twr-k60n512, twr-k70f120m: lower Ethernet link up/Tx timeout · 75b99c96
      Alexander Potashev authored
      Lower the Link UP and Ethernet transmit timeout to about 2 seconds.
  24. 25 Jan, 2012 6 commits
  25. 20 Jan, 2012 2 commits
  26. 19 Jan, 2012 1 commit
  27. 17 Jan, 2012 2 commits
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: configure DDR memory controller · f9fec77e
      Alexander Potashev authored
      Take the DDR controller configuration (including memory timings) from
      the Freescale's sample code package (KINETIS_120MHZ_SC.zip).
      Move `struct kinetis_sim_regs` to
      `include/asm-arm/arch-kinetis/kinetis.h`, because the SIM registers
      have to be updated in order to properly configure the DDR controller for
      the given external memory chip.
      DDR works in the asynchronous mode.
      Set the DDR clock to 150 MHz (using the PLL1).
      For the board with external DDR memory, the DDR configuration code
      should be enabled using the CONFIG_KINETIS_DDR configuration option in
      the U-Boot configuration file.
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: customize the Kinetis port for TWR-K70F120M · 34d45f55
      Alexander Potashev authored
      The `board/freescale/twr-k70f120m/board.c` file was copied from
      `board/freescale/twr-k60n512/board.c` without code changes, because the
      Ethernet pin configuration is compatible on these two boards.
      `cpu/arm_cortexm3/kinetis/clock.c` was updated to support the MCG
      (Multipurpose Clock Generator) internal structure on K70 @ 120 MHz
      which is different from the MCG on K60 @ 100 MHz.
      The U-Boot configuration file (include/configs/twr-k70f120m.h) was
      copied from the corresponding file for the TWR-K60N512 board and
      customized for the TWR-K70F120M board:
          1. UART pins are different
          2. There is external RAM on the TWR-K70F120M board
          3. The in-MCU flash is 1 MB in size
          4. The clock configuration was updated (120 MHz core clock)
          5. The K70 MCU has 6 GPIO ports (instead of 5 ports on K60)
  28. 16 Jan, 2012 1 commit