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Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

In case of disabled DCACHE we previously had the only one 4GB MPU
region with 'Strongly ordered' mem type. This led to problems with
strex/ldrex instruction targeted such mem (and thus we couldn't use
these instructions).

Now we always create 2 MPU region, even if DCACHE is off. The 2nd
MPU region is mapped to external SDRAM, and has 'Normal' mem type.

This patch also changes 'write-through' caching policy to 'write-
back with write & read allocate'.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Enable D- and I-caches in STM32F7-SOM.

Increase CPU frequency up to 200MHz on STM32F7-SOM.

- Validate NOR flash, SDRAM and networking support in STM32F7 U-Boot.

Boot STM32F7-SOM up to U-Boot prompt.

Initial skeleton of the STM32F7 SOM port. The configuration builds
but hasn't been yet tried on the target.

...
Board: STM-SOM Rev Rev 2.A, www.emcraft.com
...

Signed-off-by: Greg Martin <gregm102@me.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>

 - Changed ECC layout to actual
 - Removed Freescale JFFS2 cleanmarker pages hack which disables ECC for
   the OOB writes. The controller doesn't seem support relaible OOB writes.

Environment in eNVM is disabled by default (env is in NOR Flash).
To enable, switch CONFIG_ENVM_IS_IN_ENVM in the config file.

 - Favor board configuration values for default environment
 - fixed compilation warnings

(cherry picked from commit 9243d92608ef0c356e0cd5f9ce2d409da82b2a42)

compatibility with the Linux driver.

Removed 'eimage'.

Discovery.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

With these timings, I get a BogoMIPS of 36.45 for the kernel
running from SDRAM.

the STM32F429 Discovery.

Test = mtest is passing.

to the U-Boot banner print-out.

works on USART1. The processor is running at 180MHz. The USB clock is,
presumably 48MHz. SDRAM does not work yet.

This function only makes sense if CONFIG_ENVM is on (not the case for
the STM-SOM configuration).