1. 16 Jan, 2013 1 commit
  2. 11 Jan, 2013 1 commit
  3. 13 Dec, 2012 1 commit
  4. 06 Dec, 2012 3 commits
  5. 05 Dec, 2012 1 commit
  6. 04 Dec, 2012 1 commit
    • Sergei Poselenov's avatar
      RT #80404. · 0471fa57
      Sergei Poselenov authored
      Revert "RT #80404. Added workaround for Libero bug - initialize iomuxes for"
      This reverts commit b38452d4.
      
      Removed the iomux cell initialization workaround, found the real fix -
      the FPGA_RPRG pin was incorrectly pulled down on the M2S-SOM module.
      0471fa57
  7. 03 Dec, 2012 1 commit
  8. 02 Dec, 2012 1 commit
  9. 30 Nov, 2012 3 commits
  10. 29 Nov, 2012 1 commit
  11. 28 Nov, 2012 2 commits
  12. 27 Nov, 2012 1 commit
  13. 26 Nov, 2012 1 commit
  14. 23 Nov, 2012 6 commits
  15. 21 Nov, 2012 1 commit
  16. 20 Nov, 2012 6 commits
  17. 05 Nov, 2012 1 commit
  18. 02 Nov, 2012 1 commit
  19. 02 Oct, 2012 1 commit
  20. 29 Aug, 2012 1 commit
  21. 27 Jun, 2012 1 commit
  22. 25 Jun, 2012 1 commit
    • Alexander Potashev's avatar
      RT79078. k70-som: Enable and use the RTC clock for FLL when switching to FBE mode · 0c572f22
      Alexander Potashev authored
       * In order to switch the MCG to the PLL Engaged External mode (PEE
      mode), it must pass the FLL Bypassed External mode (FBE mode) as an
      intermediate step. See section `25.4.1 MCG Mode State Diagram` on page
      656 of the K70 Reference Manual.
       * Enable and use the RTC clock for FLL when switching to the
      FLL Bypassed External mode (FBE mode). We do this in `clock_fei_to_fbe()`
      in `u-boot/cpu/arm_cortexm3/kinetis/clock.c` before switching to
      the FBE mode. This is required, because:
         * In order to switch to the PLL Engaged External mode (PEE mode), we
      must pass the FLL Bypassed External mode (FBE mode).
         * This FBE mode requires that there is a working FLL reference clock.
         * Only OSC0 clock (clock or oscillator at EXTAL0/XTAL0) or RTC clock
      (oscillator at EXTAL32/XTAL32) can be used as reference clock for FLL.
         * In the K**-SOM/DNI-ETH configuration, nothing is connected to
      EXTAL0, therefore we have to use the RTC clock as reference clock
      for FLL in the FBE mode.
       * Use RTC for FLL reference clock only on K**-SOMs, but not for
      TWR-K70F120M. To do that, we add a new U-Boot configuration option
      `KINETIS_FLLREF_RTC` that will control usage of RTC for FLL reference
      clock and define this configuration option only in
      `u-boot/include/configs/k70-som.h`.
       * Use in-MCU 20pF oscillator load.
      0c572f22
  23. 18 Jun, 2012 2 commits
  24. 14 Jun, 2012 1 commit
    • Alexander Potashev's avatar
      RT77788. k70-som: Support both 120MHz and 150MHz K61/K70 MCUs · db597b14
      Alexander Potashev authored
       * Add build-time U-Boot option CONFIG_KINETIS_120MHZ or
      CONFIG_KINETIS_150MHZ to define the maximum core clock rate of the MCU.
       * Use different PLL configurations to reach to maximum clock rates and
      performance.
       * Use different LPDDR timings depending on the clock rate.
       * Use different clock dividers for internal flash and external NAND
      flash, as required by the respective datasheets.
      db597b14